unstable-riscv feature

romancardenas · romancardenas · commit ddc3d99e9aea · 2024-07-03T14:42:08.000+02:00
diff --git a/svd-encoder/CHANGELOG.md b/svd-encoder/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## Unreleased
 
 - Add `riscv` element for configuration parameters related to RISC-V targets.
+  You must use the `unstable-riscv` feature to enable this exeperimental element.
 - Bump MSRV to 1.65.0
 
 ## [v0.14.3] - 2023-11-15
diff --git a/svd-encoder/Cargo.toml b/svd-encoder/Cargo.toml
@@ -11,6 +11,9 @@ rust-version = "1.65.0"
 version = "0.14.4"
 readme = "README.md"
 
+[features]
+unstable-riscv = ["svd-rs/unstable-riscv"]
+
 [dependencies]
 convert_case = "0.6.0"
 svd-rs = { version = "0.14.7", path = "../svd-rs" }
diff --git a/svd-encoder/src/device.rs b/svd-encoder/src/device.rs
@@ -34,7 +34,7 @@ impl Encode for Device {
             elem.children.push(new_node("licenseText", v.clone()));
         }
 
-        // TODO not sure if this is the correct position
+        #[cfg(feature = "unstable-riscv")]
         if let Some(v) = &self.riscv {
             elem.children
                 .push(XMLNode::Element(v.encode_with_config(config)?));
diff --git a/svd-encoder/src/lib.rs b/svd-encoder/src/lib.rs
@@ -103,6 +103,7 @@ mod readaction;
 mod register;
 mod registercluster;
 mod registerproperties;
+#[cfg(feature = "unstable-riscv")]
 mod riscv;
 mod usage;
 mod writeconstraint;
diff --git a/svd-encoder/src/riscv.rs b/svd-encoder/src/riscv.rs
@@ -7,15 +7,6 @@ impl Encode for Riscv {
     fn encode_with_config(&self, config: &Config) -> Result<Element, EncodeError> {
         let mut elem = Element::new("riscv");
 
-        if let Some(clic) = &self.clic {
-            elem.children.push(new_node("clic", clic.clone()));
-        }
-        if let Some(clint) = &self.clint {
-            elem.children.push(new_node("clint", clint.clone()));
-        }
-        if let Some(plic) = &self.plic {
-            elem.children.push(new_node("plic", plic.clone()));
-        }
         if !self.core_interrupts.is_empty() {
             let mut interrupts = Element::new("coreInterrupts");
             for interrupt in &self.core_interrupts {
diff --git a/svd-parser/CHANGELOG.md b/svd-parser/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## Unreleased
 
 - Add `riscv` element for configuration parameters related to RISC-V targets.
+  You must use the `unstable-riscv` feature to enable this exeperimental element.
 - Bump MSRV to 1.65.0
 
 ## [v0.14.5] - 2024-01-03
diff --git a/svd-parser/Cargo.toml b/svd-parser/Cargo.toml
@@ -17,6 +17,7 @@ readme = "README.md"
 [features]
 derive-from = ["svd-rs/derive-from"]
 expand = ["derive-from"]
+unstable-riscv = ["svd-rs/unstable-riscv"]
 
 [dependencies]
 svd-rs = { version = "0.14.7", path = "../svd-rs" }
diff --git a/svd-parser/src/device.rs b/svd-parser/src/device.rs
@@ -1,7 +1,7 @@
 use super::*;
-use crate::svd::{
-    cpu::Cpu, peripheral::Peripheral, registerproperties::RegisterProperties, riscv::Riscv,
-};
+#[cfg(feature = "unstable-riscv")]
+use crate::svd::riscv::Riscv;
+use crate::svd::{cpu::Cpu, peripheral::Peripheral, registerproperties::RegisterProperties};
 
 /// Parses a SVD file
 impl Parse for Device {
@@ -20,7 +20,6 @@ impl Parse for Device {
             .name(tree.get_child_text("name")?)
             .series(tree.get_child_text_opt("series")?)
             .license_text(tree.get_child_text_opt("licenseText")?)
-            .riscv(optional::<Riscv>("riscv", tree, config)?)
             .cpu(optional::<Cpu>("cpu", tree, config)?)
             .header_system_filename(tree.get_child_text_opt("headerSystemFilename")?)
             .header_definitions_prefix(tree.get_child_text_opt("headerDefinitionsPrefix")?)
@@ -34,6 +33,10 @@ impl Parse for Device {
                     .collect();
                 ps?
             });
+        #[cfg(feature = "unstable-riscv")]
+        if let Some(riscv) = optional::<Riscv>("riscv", tree, config)? {
+            device = device.riscv(riscv);
+        }
         if let Some(version) = tree.get_child_text_opt("version")? {
             device = device.version(version)
         }
diff --git a/svd-parser/src/lib.rs b/svd-parser/src/lib.rs
@@ -211,6 +211,7 @@ mod readaction;
 mod register;
 mod registercluster;
 mod registerproperties;
+#[cfg(feature = "unstable-riscv")]
 mod riscv;
 mod usage;
 mod writeconstraint;
diff --git a/svd-parser/src/riscv.rs b/svd-parser/src/riscv.rs
@@ -11,10 +11,7 @@ impl Parse for Riscv {
             return Err(SVDError::NotExpectedTag("riscv".to_string()).at(tree.id()));
         }
 
-        let mut builder = Riscv::builder()
-            .clic(tree.get_child_text("clic").ok())
-            .clint(tree.get_child_text("clint").ok())
-            .plic(tree.get_child_text("plic").ok());
+        let mut builder = Riscv::builder();
 
         if let Some(interrupts) = tree.get_child("coreInterrupts") {
             let interrupts: Result<Vec<_>, _> = interrupts
diff --git a/svd-rs/CHANGELOG.md b/svd-rs/CHANGELOG.md
@@ -8,6 +8,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ## Unreleased
 
 - Add `riscv` element for configuration parameters related to RISC-V targets.
+  You must use the `unstable-riscv` feature to enable this exeperimental element.
 - Add `DataType`
 
 ## [v0.14.8] - 2024-02-13
diff --git a/svd-rs/Cargo.toml b/svd-rs/Cargo.toml
@@ -15,6 +15,7 @@ readme = "README.md"
 
 [features]
 derive-from = []
+unstable-riscv = []
 
 [dependencies]
 thiserror = "1.0.31"
diff --git a/svd-rs/src/device.rs b/svd-rs/src/device.rs
@@ -1,6 +1,8 @@
+#[cfg(feature = "unstable-riscv")]
+use super::Riscv;
 use super::{
-    BuildError, Cpu, Description, EmptyToNone, Name, Peripheral, RegisterProperties, Riscv,
-    SvdError, ValidateLevel,
+    BuildError, Cpu, Description, EmptyToNone, Name, Peripheral, RegisterProperties, SvdError,
+    ValidateLevel,
 };
 
 /// Errors for [`Device::validate`]
@@ -111,6 +113,7 @@ pub struct Device {
         feature = "serde",
         serde(default, skip_serializing_if = "Option::is_none")
     )]
+    #[cfg(feature = "unstable-riscv")]
     pub riscv: Option<Riscv>,
 }
 
@@ -137,6 +140,7 @@ pub struct DeviceBuilder {
     version: Option<String>,
     description: Option<String>,
     license_text: Option<String>,
+    #[cfg(feature = "unstable-riscv")]
     riscv: Option<Riscv>,
     cpu: Option<Cpu>,
     header_system_filename: Option<String>,
@@ -160,6 +164,7 @@ impl From<Device> for DeviceBuilder {
             version: Some(d.version),
             description: Some(d.description),
             license_text: d.license_text,
+            #[cfg(feature = "unstable-riscv")]
             riscv: d.riscv,
             cpu: d.cpu,
             header_system_filename: d.header_system_filename,
@@ -212,8 +217,9 @@ impl DeviceBuilder {
         self
     }
     /// Set the riscv of the device.
-    pub fn riscv(mut self, value: Option<Riscv>) -> Self {
-        self.riscv = value;
+    #[cfg(feature = "unstable-riscv")]
+    pub fn riscv(mut self, value: Riscv) -> Self {
+        self.riscv = Some(value);
         self
     }
     /// Set the cpu of the device.
@@ -297,6 +303,7 @@ impl DeviceBuilder {
                 })
                 .ok_or_else(|| BuildError::Uninitialized("description".to_string()))?,
             license_text: self.license_text,
+            #[cfg(feature = "unstable-riscv")]
             riscv: self.riscv,
             cpu: self.cpu,
             header_system_filename: self.header_system_filename,
@@ -356,6 +363,7 @@ impl Device {
         if builder.license_text.is_some() {
             self.license_text = builder.license_text.empty_to_none();
         }
+        #[cfg(feature = "unstable-riscv")]
         if builder.riscv.is_some() {
             self.riscv = builder.riscv;
         }
diff --git a/svd-rs/src/lib.rs b/svd-rs/src/lib.rs
@@ -95,7 +95,9 @@ pub mod datatype;
 pub use self::datatype::DataType;
 
 /// Custom objects for the RISC-V ecosystem
+#[cfg(feature = "unstable-riscv")]
 pub mod riscv;
+#[cfg(feature = "unstable-riscv")]
 pub use self::riscv::Riscv;
 
 /// Level of validation
diff --git a/svd-rs/src/riscv.rs b/svd-rs/src/riscv.rs
@@ -18,27 +18,6 @@ pub use priority::Priority;
 #[derive(Clone, Debug, PartialEq, Eq)]
 #[non_exhaustive]
 pub struct Riscv {
-    /// Indicate the ID of the CLIC peripheral (if present).
-    #[cfg_attr(
-        feature = "serde",
-        serde(default, skip_serializing_if = "Option::is_none")
-    )]
-    pub clic: Option<String>,
-
-    /// Indicate the ID of the CLINT peripheral (if present).
-    #[cfg_attr(
-        feature = "serde",
-        serde(default, skip_serializing_if = "Option::is_none")
-    )]
-    pub clint: Option<String>,
-
-    /// Indicate the ID of the PLIC peripheral (if present).
-    #[cfg_attr(
-        feature = "serde",
-        serde(default, skip_serializing_if = "Option::is_none")
-    )]
-    pub plic: Option<String>,
-
     /// Core interrupt enumeration values
     #[cfg_attr(
         feature = "serde",
@@ -64,9 +43,6 @@ pub struct Riscv {
 /// Builder for [`Riscv`]
 #[derive(Clone, Debug, Default, PartialEq, Eq)]
 pub struct RiscvBuilder {
-    clic: Option<String>,
-    clint: Option<String>,
-    plic: Option<String>,
     core_interrupts: Option<Vec<Interrupt>>,
     priorities: Option<Vec<Priority>>,
     harts: Option<Vec<Hart>>,
@@ -75,9 +51,6 @@ pub struct RiscvBuilder {
 impl From<Riscv> for RiscvBuilder {
     fn from(riscv: Riscv) -> Self {
         Self {
-            clic: riscv.clic,
-            clint: riscv.clint,
-            plic: riscv.plic,
             core_interrupts: Some(riscv.core_interrupts),
             priorities: Some(riscv.priorities),
             harts: Some(riscv.harts),
@@ -86,24 +59,6 @@ impl From<Riscv> for RiscvBuilder {
 }
 
 impl RiscvBuilder {
-    /// Set the ID of the CLIC peripheral
-    pub fn clic(mut self, clic: Option<String>) -> Self {
-        self.clic = clic;
-        self
-    }
-
-    /// Set the ID of the CLINT peripheral
-    pub fn clint(mut self, clint: Option<String>) -> Self {
-        self.clint = clint;
-        self
-    }
-
-    /// Set the ID of the PLIC peripheral
-    pub fn plic(mut self, plic: Option<String>) -> Self {
-        self.plic = plic;
-        self
-    }
-
     /// Set the core interrupt enumeration values
     pub fn core_interrupts(mut self, core_interrupts: Vec<Interrupt>) -> Self {
         self.core_interrupts = Some(core_interrupts);
@@ -125,9 +80,6 @@ impl RiscvBuilder {
     /// Validate and build a [`Riscv`].
     pub fn build(self, lvl: ValidateLevel) -> Result<Riscv, SvdError> {
         let riscv = Riscv {
-            clic: self.clic,
-            clint: self.clint,
-            plic: self.plic,
             core_interrupts: self
                 .core_interrupts
                 .ok_or_else(|| BuildError::Uninitialized("core_interrupts".to_string()))?,
@@ -155,15 +107,6 @@ impl Riscv {
         builder: RiscvBuilder,
         lvl: ValidateLevel,
     ) -> Result<(), SvdError> {
-        if builder.clic.is_some() {
-            self.clic = builder.clic;
-        }
-        if builder.clint.is_some() {
-            self.clint = builder.clint;
-        }
-        if builder.plic.is_some() {
-            self.plic = builder.plic;
-        }
         if let Some(core_interrupts) = builder.core_interrupts {
             self.core_interrupts = core_interrupts;
         }
diff --git a/tests/Cargo.toml b/tests/Cargo.toml
@@ -7,6 +7,9 @@ edition = "2021"
 version = "0.12.0"
 publish = false
 
+[features]
+unstable-riscv = ["svd-rs/unstable-riscv", "svd-parser/unstable-riscv", "svd-encoder/unstable-riscv"]
+
 [dependencies]
 svd-rs = { path = "../svd-rs"}
 svd-parser = { path = "../svd-parser"}
diff --git a/tests/src/lib.rs b/tests/src/lib.rs
@@ -62,4 +62,5 @@ mod register;
 mod usage;
 mod writeconstraint;
 
+#[cfg(feature = "unstable-riscv")]
 mod riscv;
diff --git a/tests/src/riscv.rs b/tests/src/riscv.rs
@@ -1,5 +1,3 @@
-use std::vec;
-
 use super::run_test;
 use crate::svd::{
     riscv::{Hart, Priority, Riscv},
@@ -89,17 +87,13 @@ fn decode_encode() {
 
     let tests = vec![(
         Riscv::builder()
-            .clint(Some("CLINT".to_string()))
-            .plic(Some("PLIC".to_string()))
             .core_interrupts(interrupts)
             .priorities(priorities)
             .harts(harts)
             .build(ValidateLevel::Strict)
             .unwrap(),
         "
                 <riscv>
-                    <clint>CLINT</clint>  
-                    <plic>PLIC</plic>
                     <coreInterrupts>
                         <interrupt>
                             <name>MachineSoft</name>
@@ -170,8 +164,6 @@ fn decode_encode() {
             ",
         "
                 <riscv>
-                    <clint>CLINT</clint>  
-                    <plic>PLIC</plic>
                     <coreInterrupts>
                         <interrupt>
                             <name>MachineSoft</name>

Original file line number	Diff line number	Diff line change
`@@ -34,7 +34,7 @@ impl Encode for Device {`
`34`	`34`	`elem.children.push(new_node("licenseText", v.clone()));`
`35`	`35`	`}`
`36`	`36`
`37`		`- // TODO not sure if this is the correct position`
	`37`	`+ #[cfg(feature = "unstable-riscv")]`
`38`	`38`	`if let Some(v) = &self.riscv {`
`39`	`39`	`elem.children`
`40`	`40`	`.push(XMLNode::Element(v.encode_with_config(config)?));`