Update nix and bitflags + bump MSRV to 1.56.1

Author: eldruin

CHANGELOG.md

@@ -4,6 +4,9 @@
 
 [Full Changelog](https://github.com/rust-embedded/rust-spidev/compare/0.5.2...HEAD)
 
+- Nix updated to 0.26
+- bitflags updated to 2.3
+- Minimum Supported Rust Version is now 1.56.1
 
 ## 0.5.2 / 2023-08-02
 

Cargo.toml

@@ -20,5 +20,5 @@ half-duplex SPI access, and full-duplex SPI access.
 
 [dependencies]
 libc = "0.2"
-bitflags = "1.3"
-nix = "0.23"
+bitflags = "2.3"
+nix = "0.26"

README.md

@@ -3,6 +3,7 @@
 [![Build Status](https://github.com/rust-embedded/rust-spidev/workflows/CI/badge.svg)](https://github.com/rust-embedded/rust-spidev/actions)
 [![Version](https://img.shields.io/crates/v/spidev.svg)](https://crates.io/crates/spidev)
 [![License](https://img.shields.io/crates/l/spidev.svg)](https://github.com/rust-embedded/rust-spidev/blob/master/README.md#license)
+![Minimum Supported Rust Version](https://img.shields.io/badge/rustc-1.56.1+-blue.svg)
 
 [Documentation](https://docs.rs/spidev)
 
@@ -76,7 +77,7 @@ The following features are implemented and planned for the library:
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.46 and up.  It *might*
+This crate is guaranteed to compile on stable Rust 1.56.1 and up.  It *might*
 compile with older versions but that may change in any new patch release.
 
 ## Cross Compiling

src/lib.rs

@@ -77,6 +77,7 @@ use std::path::Path;
 
 // Constants extracted from linux/spi/spidev.h
 bitflags! {
+    #[derive(Debug, Clone, Copy, PartialEq, Eq, PartialOrd, Ord, Hash)]
     pub struct SpiModeFlags: u32 {
         /// Clock Phase
         const SPI_CPHA = 0x01;
@@ -97,9 +98,9 @@ bitflags! {
 
         // Common Configurations
         const SPI_MODE_0 = 0x00;
-        const SPI_MODE_1 = Self::SPI_CPHA.bits;
-        const SPI_MODE_2 = Self::SPI_CPOL.bits;
-        const SPI_MODE_3 = (Self::SPI_CPOL.bits | Self::SPI_CPHA.bits);
+        const SPI_MODE_1 = Self::SPI_CPHA.bits();
+        const SPI_MODE_2 = Self::SPI_CPOL.bits();
+        const SPI_MODE_3 = (Self::SPI_CPOL.bits() | Self::SPI_CPHA.bits());
 
         // == Only Supported with 32-bits ==
 

src/spidevioctl.rs

@@ -196,10 +196,10 @@ pub fn set_mode(fd: RawFd, mode: SpiModeFlags) -> io::Result<()> {
     // the 8-bit mask are used.  This is because WR_MODE32 was not
     // added until later kernels.  This provides a reasonable story
     // for forwards and backwards compatibility
-    if (mode.bits & 0xFFFFFF00) != 0 {
-        from_nix_result(unsafe { ioctl::set_mode32(fd, &mode.bits) })?;
+    if (mode.bits() & 0xFFFFFF00) != 0 {
+        from_nix_result(unsafe { ioctl::set_mode32(fd, &mode.bits()) })?;
     } else {
-        let bits: u8 = mode.bits as u8;
+        let bits: u8 = mode.bits() as u8;
         from_nix_result(unsafe { ioctl::set_mode(fd, &bits) })?;
     }
     Ok(())