From c287260674daa8a18db49b17553e406eb66a7469 Mon Sep 17 00:00:00 2001 From: gibbz00 Date: Sun, 29 Jun 2025 09:28:47 +0200 Subject: [PATCH 1/3] docs: fix spelling with `typos` --- riscv-peripheral/src/plic.rs | 2 +- riscv-rt/build.rs | 2 +- riscv-rt/src/asm.rs | 2 +- riscv-rt/src/lib.rs | 8 ++++---- riscv/src/register/macros.rs | 6 +++--- 5 files changed, 10 insertions(+), 10 deletions(-) diff --git a/riscv-peripheral/src/plic.rs b/riscv-peripheral/src/plic.rs index f8f7728a..af0300b8 100644 --- a/riscv-peripheral/src/plic.rs +++ b/riscv-peripheral/src/plic.rs @@ -24,7 +24,7 @@ pub unsafe trait Plic: Copy { const BASE: usize; } -/// Platform-Level Interrupt Controler (PLIC) peripheral. +/// Platform-Level Interrupt Controller (PLIC) peripheral. /// /// The RISC-V standard does not specify a fixed location for the PLIC. /// Thus, each platform must specify the base address of the PLIC on the platform. diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs index 51a4cefc..e1da2d15 100644 --- a/riscv-rt/build.rs +++ b/riscv-rt/build.rs @@ -58,7 +58,7 @@ fn main() { if let Ok(target) = RiscvTarget::build(&target, &cargo_flags) { let width = target.width(); - // set environmet variable RISCV_RT_BASE_ISA to the base ISA of the target. + // set environment variable RISCV_RT_BASE_ISA to the base ISA of the target. println!( "cargo:rustc-env=RISCV_RT_BASE_ISA={}", target.llvm_base_isa() diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs index 3b25dc53..35ec3869 100644 --- a/riscv-rt/src/asm.rs +++ b/riscv-rt/src/asm.rs @@ -168,7 +168,7 @@ cfg_global_asm!( addi t0, t0, 8 bltu t0, t2, 3b", " -4: // RAM initilized", +4: // RAM initialized", ); // INITIALIZE FLOATING POINT UNIT diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs index 08c87927..498c46a3 100644 --- a/riscv-rt/src/lib.rs +++ b/riscv-rt/src/lib.rs @@ -389,7 +389,7 @@ //! //! ## `ExceptionHandler` //! -//! This function is called when exception without defined exception handler is occured. +//! This function is called when exception without defined exception handler is occurred. //! The exception reason can be decoded from the `mcause`/`scause` register. //! //! This function can be redefined in the following way: @@ -412,7 +412,7 @@ //! //! ## Core interrupt handlers //! -//! This functions are called when corresponding interrupt is occured. +//! This functions are called when corresponding interrupt is occurred. //! You can define a core interrupt handler with the [`core_interrupt`] attribute. //! The attribute expects the path to the interrupt source as an argument. //! @@ -441,7 +441,7 @@ //! //! ## External interrupt handlers //! -//! This functions are called when corresponding interrupt is occured. +//! This functions are called when corresponding interrupt is occurred. //! You can define an external interrupt handler with the [`external_interrupt`] attribute. //! The attribute expects the path to the interrupt source as an argument. //! @@ -453,7 +453,7 @@ //! //! ## `DefaultHandler` //! -//! This function is called when interrupt without defined interrupt handler is occured. +//! This function is called when interrupt without defined interrupt handler is occurred. //! The interrupt reason can be decoded from the `mcause`/`scause` register. //! If it is an external interrupt, the interrupt reason can be decoded from a //! target-specific peripheral interrupt controller. diff --git a/riscv/src/register/macros.rs b/riscv/src/register/macros.rs index c9b6254f..b5c9ee8e 100644 --- a/riscv/src/register/macros.rs +++ b/riscv/src/register/macros.rs @@ -721,7 +721,7 @@ macro_rules! write_only_csr { }; } -/// Defines field accesor functions for a read-write CSR type. +/// Defines field accessor functions for a read-write CSR type. #[macro_export] macro_rules! read_write_csr_field { ($ty:ident, @@ -804,7 +804,7 @@ macro_rules! read_write_csr_field { }; } -/// Defines field accesor functions for a read-only CSR type. +/// Defines field accessor functions for a read-only CSR type. #[macro_export] macro_rules! read_only_csr_field { ($ty:ident, @@ -899,7 +899,7 @@ macro_rules! read_only_csr_field { }; } -/// Defines field accesor functions for a write-only CSR type. +/// Defines field accessor functions for a write-only CSR type. #[macro_export] macro_rules! write_only_csr_field { ($ty:ident, From 6bb1ab0093545ec486a29f12797d74ebf0e9c587 Mon Sep 17 00:00:00 2001 From: gibbz00 Date: Sun, 29 Jun 2025 10:05:53 +0200 Subject: [PATCH 2/3] ci: add typos workflow --- .github/workflows/typos.yaml | 16 ++++++++++++++++ typos.toml | 2 ++ 2 files changed, 18 insertions(+) create mode 100644 .github/workflows/typos.yaml create mode 100644 typos.toml diff --git a/.github/workflows/typos.yaml b/.github/workflows/typos.yaml new file mode 100644 index 00000000..d3f2cf33 --- /dev/null +++ b/.github/workflows/typos.yaml @@ -0,0 +1,16 @@ +on: + push: + branches: [ master ] + pull_request: + merge_group: + +name: Spelling Check + +jobs: + spelling: + runs-on: ubuntu-latest + steps: + - name: Checkout sources + uses: actions/checkout@v4 + - name: typos + uses: crate-ci/typos@master diff --git a/typos.toml b/typos.toml new file mode 100644 index 00000000..5d4135b6 --- /dev/null +++ b/typos.toml @@ -0,0 +1,2 @@ +[default] +extend-ignore-re = ["[Ss][Ii][Ee]", "[Ss][Xx][Ll]"] From 015796aba82b20d947a0136c3e3c06436f898677 Mon Sep 17 00:00:00 2001 From: gibbz00 Date: Mon, 30 Jun 2025 10:38:44 +0200 Subject: [PATCH 3/3] ci: temporarily allow nightly lints to fail --- .github/workflows/clippy.yaml | 4 ++++ 1 file changed, 4 insertions(+) diff --git a/.github/workflows/clippy.yaml b/.github/workflows/clippy.yaml index abeb7413..7d55bcb4 100644 --- a/.github/workflows/clippy.yaml +++ b/.github/workflows/clippy.yaml @@ -37,6 +37,10 @@ jobs: strategy: matrix: toolchain: [ stable, nightly ] + include: + # Nightly is only for reference and allowed to fail + - toolchain: nightly + experimental: true runs-on: ubuntu-latest continue-on-error: ${{ matrix.experimental || false }} steps: