diff --git a/.github/workflows/clippy.yaml b/.github/workflows/clippy.yaml
index abeb7413..7d55bcb4 100644
--- a/.github/workflows/clippy.yaml
+++ b/.github/workflows/clippy.yaml
@@ -37,6 +37,10 @@ jobs:
     strategy:
       matrix:
         toolchain: [ stable, nightly ]
+        include:
+          # Nightly is only for reference and allowed to fail
+          - toolchain: nightly
+            experimental: true
     runs-on: ubuntu-latest
     continue-on-error: ${{ matrix.experimental || false }}
     steps:
diff --git a/.github/workflows/typos.yaml b/.github/workflows/typos.yaml
new file mode 100644
index 00000000..d3f2cf33
--- /dev/null
+++ b/.github/workflows/typos.yaml
@@ -0,0 +1,16 @@
+on:
+  push:
+    branches: [ master ]
+  pull_request:
+  merge_group:
+
+name: Spelling Check
+
+jobs:
+  spelling:
+    runs-on: ubuntu-latest
+    steps:
+    - name: Checkout sources
+      uses: actions/checkout@v4
+    - name: typos
+      uses: crate-ci/typos@master
diff --git a/riscv-peripheral/src/plic.rs b/riscv-peripheral/src/plic.rs
index f8f7728a..af0300b8 100644
--- a/riscv-peripheral/src/plic.rs
+++ b/riscv-peripheral/src/plic.rs
@@ -24,7 +24,7 @@ pub unsafe trait Plic: Copy {
     const BASE: usize;
 }
 
-/// Platform-Level Interrupt Controler (PLIC) peripheral.
+/// Platform-Level Interrupt Controller (PLIC) peripheral.
 ///
 /// The RISC-V standard does not specify a fixed location for the PLIC.
 /// Thus, each platform must specify the base address of the PLIC on the platform.
diff --git a/riscv-rt/build.rs b/riscv-rt/build.rs
index 51a4cefc..e1da2d15 100644
--- a/riscv-rt/build.rs
+++ b/riscv-rt/build.rs
@@ -58,7 +58,7 @@ fn main() {
     if let Ok(target) = RiscvTarget::build(&target, &cargo_flags) {
         let width = target.width();
 
-        // set environmet variable RISCV_RT_BASE_ISA to the base ISA of the target.
+        // set environment variable RISCV_RT_BASE_ISA to the base ISA of the target.
         println!(
             "cargo:rustc-env=RISCV_RT_BASE_ISA={}",
             target.llvm_base_isa()
diff --git a/riscv-rt/src/asm.rs b/riscv-rt/src/asm.rs
index 3b25dc53..35ec3869 100644
--- a/riscv-rt/src/asm.rs
+++ b/riscv-rt/src/asm.rs
@@ -168,7 +168,7 @@ cfg_global_asm!(
     addi t0, t0, 8
     bltu t0, t2, 3b",
     "
-4: // RAM initilized",
+4: // RAM initialized",
 );
 
 // INITIALIZE FLOATING POINT UNIT
diff --git a/riscv-rt/src/lib.rs b/riscv-rt/src/lib.rs
index 08c87927..498c46a3 100644
--- a/riscv-rt/src/lib.rs
+++ b/riscv-rt/src/lib.rs
@@ -389,7 +389,7 @@
 //!
 //! ## `ExceptionHandler`
 //!
-//! This function is called when exception without defined exception handler is occured.
+//! This function is called when exception without defined exception handler is occurred.
 //! The exception reason can be decoded from the `mcause`/`scause` register.
 //!
 //! This function can be redefined in the following way:
@@ -412,7 +412,7 @@
 //!
 //! ## Core interrupt handlers
 //!
-//! This functions are called when corresponding interrupt is occured.
+//! This functions are called when corresponding interrupt is occurred.
 //! You can define a core interrupt handler with the [`core_interrupt`] attribute.
 //! The attribute expects the path to the interrupt source as an argument.
 //!
@@ -441,7 +441,7 @@
 //!
 //! ## External interrupt handlers
 //!
-//! This functions are called when corresponding interrupt is occured.
+//! This functions are called when corresponding interrupt is occurred.
 //! You can define an external interrupt handler with the [`external_interrupt`] attribute.
 //! The attribute expects the path to the interrupt source as an argument.
 //!
@@ -453,7 +453,7 @@
 //!
 //! ## `DefaultHandler`
 //!
-//! This function is called when interrupt without defined interrupt handler is occured.
+//! This function is called when interrupt without defined interrupt handler is occurred.
 //! The interrupt reason can be decoded from the `mcause`/`scause` register.
 //! If it is an external interrupt, the interrupt reason can be decoded from a
 //! target-specific peripheral interrupt controller.
diff --git a/riscv/src/register/macros.rs b/riscv/src/register/macros.rs
index c9b6254f..b5c9ee8e 100644
--- a/riscv/src/register/macros.rs
+++ b/riscv/src/register/macros.rs
@@ -721,7 +721,7 @@ macro_rules! write_only_csr {
     };
 }
 
-/// Defines field accesor functions for a read-write CSR type.
+/// Defines field accessor functions for a read-write CSR type.
 #[macro_export]
 macro_rules! read_write_csr_field {
     ($ty:ident,
@@ -804,7 +804,7 @@ macro_rules! read_write_csr_field {
     };
 }
 
-/// Defines field accesor functions for a read-only CSR type.
+/// Defines field accessor functions for a read-only CSR type.
 #[macro_export]
 macro_rules! read_only_csr_field {
     ($ty:ident,
@@ -899,7 +899,7 @@ macro_rules! read_only_csr_field {
     };
 }
 
-/// Defines field accesor functions for a write-only CSR type.
+/// Defines field accessor functions for a write-only CSR type.
 #[macro_export]
 macro_rules! write_only_csr_field {
     ($ty:ident,
diff --git a/typos.toml b/typos.toml
new file mode 100644
index 00000000..5d4135b6
--- /dev/null
+++ b/typos.toml
@@ -0,0 +1,2 @@
+[default]
+extend-ignore-re = ["[Ss][Ii][Ee]", "[Ss][Xx][Ll]"]