Merge #48

48: Remove vexriscv support. r=Disasm a=khrs



Co-authored-by: Karol Harasim <karol.harasim@gmail.com>

Author: bors[bot]

CHANGELOG.md

@@ -12,6 +12,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 - Updated Minimum Supported Rust Version to 1.31.0
 - Use `llvm_asm!` instead of `asm!`
 
+### Removed
+
+- vexriscv-specific registers were moved to the `vexriscv` crate
+
 ## [v0.5.6] - 2020-03-14
 
 ### Added

asm.S

@@ -273,10 +273,3 @@ RW(0x7A3, tdata3)   // Third Debug/Trace trigger data register
 RW(0x7B0, dcsr)     // Debug control and status register
 RW(0x7B1, dpc)      // Debug PC
 RW(0x7B2, dscratch) // Debug scratch register
-
-// VexRiscv custom registers
-RW(0xBC0, vmim)     // Machine IRQ Mask
-RO(0xFC0, vmip)     // Machine IRQ Pending
-RW(0x9C0, vsim)     // Supervisor IRQ Mask
-RO(0xDC0, vsip)     // Supervisor IRQ Pending
-RO(0xCC0, vdci)     // DCache Info

bin/riscv32i-unknown-none-elf.a

@@ -98,6 +98,3 @@ pub use self::mhpmeventx::*;
 // TODO: Debug/Trace Registers (shared with Debug Mode)
 
 // TODO: Debug Mode Registers
-
-// Vexriscv custom CSRs
-pub mod vexriscv;