Skip to content

Commit fec65d8

Browse files
committed
Add write function for {u,s}{cause,tval} registers
1 parent 4145e4a commit fec65d8

File tree

4 files changed

+54
-0
lines changed

4 files changed

+54
-0
lines changed

src/register/scause.rs

Lines changed: 36 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -115,3 +115,39 @@ impl Scause {
115115
}
116116

117117
read_csr_as!(Scause, 0x142, __read_scause);
118+
write_csr!(0x142, __write_scause);
119+
120+
/// Writes the CSR
121+
pub unsafe fn write(bits: usize) {
122+
_write(bits)
123+
}
124+
125+
/// Set supervisor cause register to corresponding cause.
126+
pub unsafe fn set(cause: Trap) {
127+
let bits = match cause {
128+
Trap::Interrupt(i) => match i {
129+
Interrupt::UserSoft => 0,
130+
Interrupt::SupervisorSoft => 1,
131+
Interrupt::UserTimer => 4,
132+
Interrupt::SupervisorTimer => 5,
133+
Interrupt::UserExternal => 8,
134+
Interrupt::SupervisorExternal => 9,
135+
Interrupt::Unknown => panic!("unknown interrupt")
136+
},
137+
Trap::Exception(e) => (match e {
138+
Exception::InstructionMisaligned => 0,
139+
Exception::InstructionFault => 1,
140+
Exception::IllegalInstruction => 2,
141+
Exception::Breakpoint => 3,
142+
Exception::LoadFault => 5,
143+
Exception::StoreMisaligned => 6,
144+
Exception::StoreFault => 7,
145+
Exception::UserEnvCall => 8,
146+
Exception::InstructionPageFault => 12,
147+
Exception::LoadPageFault => 13,
148+
Exception::StorePageFault => 15,
149+
Exception::Unknown => panic!("unknown exception")
150+
} | (1 << (size_of::<usize>() * 8 - 1))),
151+
};
152+
_write(bits);
153+
}

src/register/stval.rs

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,9 @@
11
//! stval register
22
33
read_csr_as_usize!(0x143, __read_stval);
4+
write_csr!(0x143, __write_stval);
5+
6+
/// Writes the CSR
7+
pub unsafe fn write(bits: usize) {
8+
_write(bits)
9+
}

src/register/ucause.rs

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -15,3 +15,9 @@ impl Ucause {
1515
}
1616

1717
read_csr_as!(Ucause, 0x042, __read_ucause);
18+
write_csr!(0x042, __write_ucause);
19+
20+
/// Writes the CSR
21+
pub unsafe fn write(bits: usize) {
22+
_write(bits)
23+
}

src/register/utval.rs

Lines changed: 6 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -1,3 +1,9 @@
11
//! utval register
22
33
read_csr_as_usize!(0x043, __read_utval);
4+
write_csr!(0x043, __write_utval);
5+
6+
/// Writes the CSR
7+
pub unsafe fn write(bits: usize) {
8+
_write(bits)
9+
}

0 commit comments

Comments
 (0)