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Cleanup code using cargo fmt
1 parent 97f1347 commit e5b4e1f

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4 files changed

+24
-22
lines changed

4 files changed

+24
-22
lines changed

src/register/instret.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//! instret register
2-
//!
2+
//!
33
//! Shadow of minstret register
44
//! must have `scounteren::ir` or `mcounteren::ir` bit enabled depending on whether
55
//! S-mode is implemented or not

src/register/instreth.rs

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,5 +1,5 @@
11
//! instreth register
2-
//!
2+
//!
33
//! Shadow of minstreth register (rv32)
44
//! must have `scounteren::ir` or `mcounteren::ir` bit enabled depending on whether
55
//! S-mode is implemented or not

src/register/mstatus.rs

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -166,9 +166,9 @@ impl Mstatus {
166166

167167
/// Timeout Wait
168168
///
169-
/// Indicates that if WFI instruction should be intercepted.
170-
///
171-
/// If this bit is set, when WFI is executed in S-mode, and it does not complete
169+
/// Indicates that if WFI instruction should be intercepted.
170+
///
171+
/// If this bit is set, when WFI is executed in S-mode, and it does not complete
172172
/// within an implementation specific, bounded time limit, the WFI instruction will cause
173173
/// an illegal instruction trap; or could always cause trap then the time limit is zero.
174174
///
@@ -189,7 +189,7 @@ impl Mstatus {
189189
self.bits.get_bit(22)
190190
}
191191

192-
/*
192+
/*
193193
FIXME: There are MBE and SBE bits in 1.12; once Privileged Specification version 1.12
194194
is ratified, there should be read functions of these bits as well.
195195
*/

src/register/scause.rs

Lines changed: 18 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -132,22 +132,24 @@ pub unsafe fn set(cause: Trap) {
132132
Interrupt::SupervisorTimer => 5,
133133
Interrupt::UserExternal => 8,
134134
Interrupt::SupervisorExternal => 9,
135-
Interrupt::Unknown => panic!("unknown interrupt")
136-
},
137-
Trap::Exception(e) => (match e {
138-
Exception::InstructionMisaligned => 0,
139-
Exception::InstructionFault => 1,
140-
Exception::IllegalInstruction => 2,
141-
Exception::Breakpoint => 3,
142-
Exception::LoadFault => 5,
143-
Exception::StoreMisaligned => 6,
144-
Exception::StoreFault => 7,
145-
Exception::UserEnvCall => 8,
146-
Exception::InstructionPageFault => 12,
147-
Exception::LoadPageFault => 13,
148-
Exception::StorePageFault => 15,
149-
Exception::Unknown => panic!("unknown exception")
150-
} | (1 << (size_of::<usize>() * 8 - 1))),
135+
Interrupt::Unknown => panic!("unknown interrupt"),
136+
},
137+
Trap::Exception(e) => {
138+
(match e {
139+
Exception::InstructionMisaligned => 0,
140+
Exception::InstructionFault => 1,
141+
Exception::IllegalInstruction => 2,
142+
Exception::Breakpoint => 3,
143+
Exception::LoadFault => 5,
144+
Exception::StoreMisaligned => 6,
145+
Exception::StoreFault => 7,
146+
Exception::UserEnvCall => 8,
147+
Exception::InstructionPageFault => 12,
148+
Exception::LoadPageFault => 13,
149+
Exception::StorePageFault => 15,
150+
Exception::Unknown => panic!("unknown exception"),
151+
} | (1 << (size_of::<usize>() * 8 - 1)))
152+
}
151153
};
152154
_write(bits);
153155
}

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