Adapt riscv to edition 2024

Author: romancardenas

.github/workflows/riscv.yaml

@@ -11,8 +11,8 @@ jobs:
   build-riscv:
     strategy:
       matrix:
-        # All generated code should be running on stable now, MRSV is 1.67.0
-        toolchain: [ stable, nightly, 1.67.0 ]
+        # All generated code should be running on stable now, MRSV is 1.85.0
+        toolchain: [ stable, nightly, 1.85.0 ]
         target:
           - riscv32i-unknown-none-elf
           - riscv32imc-unknown-none-elf

riscv/CHANGELOG.md

@@ -10,6 +10,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 ### Changed
 
 - Use `cfg(any(target_arch = "riscv32", target_arch = "riscv64"))` instead of `cfg(riscv)`.
+- Update to Rust edition 2024 (MSRV 1.85)
 
 ### Removed
 

riscv/Cargo.toml

@@ -1,8 +1,8 @@
 [package]
 name = "riscv"
 version = "0.14.0"
-edition = "2021"
-rust-version = "1.67"
+edition = "2024"
+rust-version = "1.85"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]

riscv/README.md

@@ -11,7 +11,7 @@ This project is developed and maintained by the [RISC-V team][team].
 
 ## Minimum Supported Rust Version (MSRV)
 
-This crate is guaranteed to compile on stable Rust 1.61 and up. It *might*
+This crate is guaranteed to compile on stable Rust 1.85 and up. It **won't**
 compile with older versions but that may change in any new patch release.
 
 ## License

riscv/macros/Cargo.toml

@@ -10,7 +10,7 @@ license = "MIT OR Apache-2.0"
 name = "riscv-macros"
 repository = "https://github.com/rust-embedded/riscv"
 version = "0.2.0"
-edition = "2021"
+edition = "2024"
 
 [lib]
 proc-macro = true

riscv/macros/src/lib.rs

@@ -4,10 +4,10 @@ use quote::quote;
 use std::collections::HashMap;
 use std::str::FromStr;
 use syn::{
+    Data, DeriveInput, Ident, Token,
     parse::{Parse, ParseStream},
     parse_macro_input,
     spanned::Spanned,
-    Data, DeriveInput, Ident, Token,
 };
 
 /// Struct to represent a function parameter.
@@ -275,7 +275,7 @@ impl PacEnumItem {
             _ => {
                 return quote!(compile_error!(
                     "RISCV_MTVEC_ALIGN is not a power of 2 (minimum 4)"
-                ))
+                ));
             }
         };
         let mut asm = format!(
@@ -373,28 +373,28 @@ core::arch::global_asm!("
             // Push the interrupt handler functions and the interrupt array
             res.push(quote! {
                 #cfg_v_trap
-                extern "C" {
+                unsafe extern "C" {
                     #(#handlers;)*
                 }
 
                 #cfg_v_trap
                 #[doc(hidden)]
-                #[no_mangle]
+                #[unsafe(no_mangle)]
                 pub static #vector_table: [Option<unsafe extern "C" fn(#(#array_signature),*)>; #max_discriminant + 1] = [
                     #(#interrupt_array),*
                 ];
 
                 #cfg_v_trap
                 #[inline]
-                #[no_mangle]
+                #[unsafe(no_mangle)]
                 unsafe extern "C" fn #dispatch_fn_name(#(#dispatch_fn_args),*) {
-                    extern "C" {
+                    unsafe extern "C" {
                         fn #default_handler(#(#extern_signature),*);
                     }
 
                     match #vector_table.get(code) {
-                        Some(Some(handler)) => handler(#(#handler_input),*),
-                        _ => #default_handler(#(#handler_input),*),
+                        Some(Some(handler)) => unsafe { handler(#(#handler_input),*) },
+                        _ => unsafe { #default_handler(#(#handler_input),*) },
                     }
                 }
             });

riscv/src/asm.rs

@@ -6,7 +6,7 @@ macro_rules! instruction {
         #[inline(always)]
         pub unsafe fn $fnname() {
             #[cfg(any(target_arch = "riscv32", target_arch = "riscv64"))]
-            core::arch::asm!($asm, $($options)*);
+            unsafe { core::arch::asm!($asm, $($options)*) };
             #[cfg(not(any(target_arch = "riscv32", target_arch = "riscv64")))]
             unimplemented!();
         }

riscv/src/critical_section.rs

@@ -1,4 +1,4 @@
-use critical_section::{set_impl, Impl, RawRestoreState};
+use critical_section::{Impl, RawRestoreState, set_impl};
 
 use crate::interrupt;
 

riscv/src/interrupt/machine.rs

@@ -3,8 +3,8 @@ use crate::{
     register::{mcause, mepc, mstatus},
 };
 use riscv_pac::{
-    result::{Error, Result},
     CoreInterruptNumber, ExceptionNumber, InterruptNumber,
+    result::{Error, Result},
 };
 
 /// Standard M-mode RISC-V interrupts
@@ -110,7 +110,7 @@ pub fn disable() {
 /// Do not call this function inside a critical section.
 #[inline]
 pub unsafe fn enable() {
-    mstatus::set_mie()
+    unsafe { mstatus::set_mie() }
 }
 
 /// Retrieves the cause of a trap in the current hart (machine mode).
@@ -181,7 +181,7 @@ where
     let mepc = mepc::read();
 
     // enable interrupts to allow nested interrupts
-    enable();
+    unsafe { enable() };
 
     let r = f();
 
@@ -193,10 +193,12 @@ where
 
     // Restore MSTATUS.PIE, MSTATUS.MPP, and SEPC
     if mstatus.mpie() {
-        mstatus::set_mpie();
+        unsafe { mstatus::set_mpie() };
     }
-    mstatus::set_mpp(mstatus.mpp());
-    mepc::write(mepc);
+    unsafe {
+        mstatus::set_mpp(mstatus.mpp());
+        mepc::write(mepc);
+    };
 
     r
 }

riscv/src/interrupt/supervisor.rs

@@ -3,8 +3,8 @@ use crate::{
     register::{scause, sepc, sstatus},
 };
 use riscv_pac::{
-    result::{Error, Result},
     CoreInterruptNumber, ExceptionNumber, InterruptNumber,
+    result::{Error, Result},
 };
 
 /// Interrupt
@@ -102,7 +102,7 @@ pub fn disable() {
 /// Do not call this function inside a critical section.
 #[inline]
 pub unsafe fn enable() {
-    sstatus::set_sie()
+    unsafe { sstatus::set_sie() }
 }
 
 /// Retrieves the cause of a trap in the current hart (supervisor mode).
@@ -173,7 +173,7 @@ where
     let sepc = sepc::read();
 
     // enable interrupts to allow nested interrupts
-    enable();
+    unsafe { enable() };
 
     let r = f();
 
@@ -185,10 +185,12 @@ where
 
     // Restore SSTATUS.SPIE, SSTATUS.SPP, and SEPC
     if sstatus.spie() {
-        sstatus::set_spie();
+        unsafe { sstatus::set_spie() };
+    }
+    unsafe {
+        sstatus::set_spp(sstatus.spp());
+        sepc::write(sepc);
     }
-    sstatus::set_spp(sstatus.spp());
-    sepc::write(sepc);
 
     r
 }