rust-embedded
diff --git a/‎riscv-rt/asm.S
Lines changed: 2 additions & 4 deletions b/‎riscv-rt/asm.S
Lines changed: 2 additions & 4 deletions
diff --git a/‎riscv-rt/bin/riscv32i-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32ic-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32if-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32ifc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32ifd-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32ifdc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32im-unknown-none-elf.a
32 Bytes b/‎riscv-rt/bin/riscv32im-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32imc-unknown-none-elf.a
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diff --git a/‎riscv-rt/bin/riscv32imf-unknown-none-elf.a
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@@ -124,11 +124,9 @@ _abs_start:
     restores caller saved registers and then returns.
 */
 .section .trap, "ax"
-.global _start_trap
-/* Make it .weak so PAC/HAL can provide their own if needed. */
-.weak _start_trap
+.global default_start_trap
 
-_start_trap:
+default_start_trap:
     addi sp, sp, -16*REGBYTES
 
     STORE ra, 0*REGBYTES(sp)