Release v0.6.0

Author: Disasm

CHANGELOG.md

@@ -7,6 +7,8 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.6.0] - 2020-06-20
+
 ### Changed
 
 - `Mtvec::trap_mode()` not returns `Option<TrapMode>` (breaking change)
@@ -37,6 +39,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 - Fixed MSRV by restricting the upper bound of `bare-metal` version
 
-[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.5.6...HEAD
+[Unreleased]: https://github.com/rust-embedded/riscv/compare/v0.6.0...HEAD
+[v0.6.0]: https://github.com/rust-embedded/riscv/compare/v0.5.6...v0.6.0
 [v0.5.6]: https://github.com/rust-embedded/riscv/compare/v0.5.5...v0.5.6
 [v0.5.5]: https://github.com/rust-embedded/riscv/compare/v0.5.4...v0.5.5

Cargo.toml

@@ -1,6 +1,6 @@
 [package]
 name = "riscv"
-version = "0.5.6"
+version = "0.6.0"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]