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lines changed Original file line number Diff line number Diff line change @@ -7,6 +7,10 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [ Unreleased]
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+ ### Added
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+
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+ - New convenience ` try_new ` and ` new ` associated functions for ` Mtvec ` and ` Stvec ` .
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### Changed
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- Use ` cfg(any(target_arch = "riscv32", target_arch = "riscv64")) ` instead of ` cfg(riscv) ` .
Original file line number Diff line number Diff line change @@ -28,6 +28,25 @@ read_write_csr_field! {
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}
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impl Mtvec {
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+ /// Creates a new `Mtvec` with the given address and trap mode.
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+ ///
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+ /// # Note
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+ ///
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+ /// Panics if the address is not aligned to 4-bytes.
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+ #[ inline]
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+ pub fn new ( address : usize , trap_mode : TrapMode ) -> Self {
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+ Self :: try_new ( address, trap_mode) . unwrap ( )
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+ }
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+
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+ /// Attempts to create a new `Mtvec` with the given address and trap mode.
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+ #[ inline]
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+ pub fn try_new ( address : usize , trap_mode : TrapMode ) -> Result < Self > {
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+ let mut mtvec = Self :: from_bits ( 0 ) ;
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+ mtvec. try_set_address ( address) ?;
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+ mtvec. set_trap_mode ( trap_mode) ;
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+ Ok ( mtvec)
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+ }
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+
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/// Returns the trap-vector base-address
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#[ inline]
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pub const fn address ( & self ) -> usize {
Original file line number Diff line number Diff line change @@ -19,6 +19,25 @@ read_write_csr_field! {
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}
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impl Stvec {
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+ /// Creates a new `Stvec` with the given address and trap mode.
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+ ///
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+ /// # Note
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+ ///
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+ /// Panics if the address is not aligned to 4-bytes.
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+ #[ inline]
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+ pub fn new ( address : usize , trap_mode : TrapMode ) -> Self {
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+ Self :: try_new ( address, trap_mode) . unwrap ( )
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+ }
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+
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+ /// Attempts to create a new `Stvec` with the given address and trap mode.
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+ #[ inline]
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+ pub fn try_new ( address : usize , trap_mode : TrapMode ) -> Result < Self > {
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+ let mut stvec = Stvec :: from_bits ( 0 ) ;
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+ stvec. try_set_address ( address) ?;
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+ stvec. set_trap_mode ( trap_mode) ;
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+ Ok ( stvec)
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+ }
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+
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/// Returns the trap-vector base-address
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#[ inline]
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pub const fn address ( & self ) -> usize {
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