Merge pull request #140 from rust-embedded/remove-bit-field

Remove bit_field dependency

Author: almindor

.gitignore

@@ -2,3 +2,4 @@ Cargo.lock
 target/
 
 .vscode/
+.DS_Store

CHANGELOG.md

@@ -16,6 +16,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ### Changed
 
+- Removed `bit_field` dependency
 - CI actions updated. They now use `checkout@v3` and `dtolnay/rust-toolchain`.
 - `mcause::{Interrupt, Exception}` and `scause::{Interrupt, Exception}` now implement `From` trait for `usize`
 - Set safety of `asm::nop` and `asm::delay` functions to safe.

Cargo.toml

@@ -23,7 +23,6 @@ critical-section-single-hart = ["critical-section/restore-state-bool"]
 plic = ["volatile-register"]
 
 [dependencies]
-bit_field = "0.10.0"
 critical-section = "1.1.0"
 embedded-hal = "0.2.6"
 volatile-register = { version  = "0.2.1", optional = true }

src/register/fcsr.rs

@@ -1,7 +1,5 @@
 //! Floating-point control and status register
 
-use bit_field::BitField;
-
 /// Floating-point control and status register
 #[derive(Clone, Copy, Debug)]
 pub struct FCSR {
@@ -35,31 +33,31 @@ impl Flags {
     /// Inexact
     #[inline]
     pub fn nx(&self) -> bool {
-        self.0.get_bit(0)
+        self.0 & (1 << 0) != 0
     }
 
     /// Underflow
     #[inline]
     pub fn uf(&self) -> bool {
-        self.0.get_bit(1)
+        self.0 & (1 << 1) != 0
     }
 
     /// Overflow
     #[inline]
     pub fn of(&self) -> bool {
-        self.0.get_bit(2)
+        self.0 & (1 << 2) != 0
     }
 
     /// Divide by Zero
     #[inline]
     pub fn dz(&self) -> bool {
-        self.0.get_bit(3)
+        self.0 & (1 << 3) != 0
     }
 
     /// Invalid Operation
     #[inline]
     pub fn nv(&self) -> bool {
-        self.0.get_bit(4)
+        self.0 & (1 << 4) != 0
     }
 }
 
@@ -84,13 +82,14 @@ impl FCSR {
     /// Accrued Exception Flags
     #[inline]
     pub fn fflags(&self) -> Flags {
-        Flags(self.bits.get_bits(0..5))
+        Flags(self.bits & 0x1F) // bits 0-4
     }
 
     /// Rounding Mode
     #[inline]
     pub fn frm(&self) -> RoundingMode {
-        match self.bits.get_bits(5..8) {
+        let frm = (self.bits >> 5) & 0x7; // bits 5-7
+        match frm {
             0b000 => RoundingMode::RoundToNearestEven,
             0b001 => RoundingMode::RoundTowardsZero,
             0b010 => RoundingMode::RoundDown,

src/register/macros.rs

@@ -229,8 +229,9 @@ macro_rules! set_pmp {
             assert!(index < 8);
 
             let mut value = _read();
+            value &= !(0xFF << (8 * index)); // clear previous value
             let byte = (locked as usize) << 7 | (range as usize) << 3 | (permission as usize);
-            value.set_bits(8 * index..=8 * index + 7, byte);
+            value |= byte << (8 * index);
             _write(value);
         }
     };
@@ -248,7 +249,7 @@ macro_rules! clear_pmp {
             assert!(index < 8);
 
             let mut value = _read();
-            value.set_bits(8 * index..=8 * index + 7, 0);
+            value &= !(0xFF << (8 * index)); // clear previous value
             _write(value);
         }
     };

src/register/mcounteren.rs

@@ -1,7 +1,5 @@
 //! mcounteren register
 
-use bit_field::BitField;
-
 /// mcounteren register
 #[derive(Clone, Copy, Debug)]
 pub struct Mcounteren {
@@ -12,26 +10,26 @@ impl Mcounteren {
     /// Supervisor "cycle\[h\]" Enable
     #[inline]
     pub fn cy(&self) -> bool {
-        self.bits.get_bit(0)
+        self.bits & (1 << 0) != 0
     }
 
     /// Supervisor "time\[h\]" Enable
     #[inline]
     pub fn tm(&self) -> bool {
-        self.bits.get_bit(1)
+        self.bits & (1 << 1) != 0
     }
 
     /// Supervisor "instret\[h\]" Enable
     #[inline]
     pub fn ir(&self) -> bool {
-        self.bits.get_bit(2)
+        self.bits & (1 << 2) != 0
     }
 
     /// Supervisor "hpm\[x\]" Enable (bits 3-31)
     #[inline]
     pub fn hpm(&self, index: usize) -> bool {
         assert!((3..32).contains(&index));
-        self.bits.get_bit(index)
+        self.bits & (1 << index) != 0
     }
 }
 

src/register/medeleg.rs

@@ -1,7 +1,5 @@
 //! medeleg register
 
-use bit_field::BitField;
-
 /// medeleg register
 #[derive(Clone, Copy, Debug)]
 pub struct Medeleg {
@@ -18,85 +16,85 @@ impl Medeleg {
     /// Instruction Address Misaligned Delegate
     #[inline]
     pub fn instruction_misaligned(&self) -> bool {
-        self.bits.get_bit(0)
+        self.bits & (1 << 0) != 0
     }
 
     /// Instruction Access Fault Delegate
     #[inline]
     pub fn instruction_fault(&self) -> bool {
-        self.bits.get_bit(1)
+        self.bits & (1 << 1) != 0
     }
 
     /// Illegal Instruction Delegate
     #[inline]
     pub fn illegal_instruction(&self) -> bool {
-        self.bits.get_bit(2)
+        self.bits & (1 << 2) != 0
     }
 
     /// Breakpoint Delegate
     #[inline]
     pub fn breakpoint(&self) -> bool {
-        self.bits.get_bit(3)
+        self.bits & (1 << 3) != 0
     }
 
     /// Load Address Misaligned Delegate
     #[inline]
     pub fn load_misaligned(&self) -> bool {
-        self.bits.get_bit(4)
+        self.bits & (1 << 4) != 0
     }
 
     /// Load Access Fault Delegate
     #[inline]
     pub fn load_fault(&self) -> bool {
-        self.bits.get_bit(5)
+        self.bits & (1 << 5) != 0
     }
 
     /// Store/AMO Address Misaligned Delegate
     #[inline]
     pub fn store_misaligned(&self) -> bool {
-        self.bits.get_bit(6)
+        self.bits & (1 << 6) != 0
     }
 
     /// Store/AMO Access Fault Delegate
     #[inline]
     pub fn store_fault(&self) -> bool {
-        self.bits.get_bit(7)
+        self.bits & (1 << 7) != 0
     }
 
     /// Environment Call from U-mode Delegate
     #[inline]
     pub fn user_env_call(&self) -> bool {
-        self.bits.get_bit(8)
+        self.bits & (1 << 8) != 0
     }
 
     /// Environment Call from S-mode Delegate
     #[inline]
     pub fn supervisor_env_call(&self) -> bool {
-        self.bits.get_bit(9)
+        self.bits & (1 << 9) != 0
     }
 
     /// Environment Call from M-mode Delegate
     #[inline]
     pub fn machine_env_call(&self) -> bool {
-        self.bits.get_bit(11)
+        self.bits & (1 << 11) != 0
     }
 
     /// Instruction Page Fault Delegate
     #[inline]
     pub fn instruction_page_fault(&self) -> bool {
-        self.bits.get_bit(12)
+        self.bits & (1 << 12) != 0
     }
 
     /// Load Page Fault Delegate
     #[inline]
     pub fn load_page_fault(&self) -> bool {
-        self.bits.get_bit(13)
+        self.bits & (1 << 13) != 0
     }
 
     /// Store/AMO Page Fault Delegate
     #[inline]
     pub fn store_page_fault(&self) -> bool {
-        self.bits.get_bit(15)
+        self.bits & (1 << 15) != 0
     }
 }
 

src/register/mideleg.rs

@@ -1,7 +1,5 @@
 //! mideleg register
 
-use bit_field::BitField;
-
 /// mideleg register
 #[derive(Clone, Copy, Debug)]
 pub struct Mideleg {
@@ -18,37 +16,37 @@ impl Mideleg {
     /// User Software Interrupt Delegate
     #[inline]
     pub fn usoft(&self) -> bool {
-        self.bits.get_bit(0)
+        self.bits & (1 << 0) != 0
     }
 
     /// Supervisor Software Interrupt Delegate
     #[inline]
     pub fn ssoft(&self) -> bool {
-        self.bits.get_bit(1)
+        self.bits & (1 << 1) != 0
     }
 
     /// User Timer Interrupt Delegate
     #[inline]
     pub fn utimer(&self) -> bool {
-        self.bits.get_bit(4)
+        self.bits & (1 << 4) != 0
     }
 
     /// Supervisor Timer Interrupt Delegate
     #[inline]
     pub fn stimer(&self) -> bool {
-        self.bits.get_bit(5)
+        self.bits & (1 << 5) != 0
     }
 
     /// User External Interrupt Delegate
     #[inline]
     pub fn uext(&self) -> bool {
-        self.bits.get_bit(8)
+        self.bits & (1 << 8) != 0
     }
 
     /// Supervisor External Interrupt Delegate
     #[inline]
     pub fn sext(&self) -> bool {
-        self.bits.get_bit(9)
+        self.bits & (1 << 9) != 0
     }
 }
 

src/register/mie.rs

@@ -1,7 +1,5 @@
 //! mie register
 
-use bit_field::BitField;
-
 /// mie register
 #[derive(Clone, Copy, Debug)]
 pub struct Mie {
@@ -18,55 +16,55 @@ impl Mie {
     /// User Software Interrupt Enable
     #[inline]
     pub fn usoft(&self) -> bool {
-        self.bits.get_bit(0)
+        self.bits & (1 << 0) != 0
     }
 
     /// Supervisor Software Interrupt Enable
     #[inline]
     pub fn ssoft(&self) -> bool {
-        self.bits.get_bit(1)
+        self.bits & (1 << 1) != 0
     }
 
     /// Machine Software Interrupt Enable
     #[inline]
     pub fn msoft(&self) -> bool {
-        self.bits.get_bit(3)
+        self.bits & (1 << 3) != 0
     }
 
     /// User Timer Interrupt Enable
     #[inline]
     pub fn utimer(&self) -> bool {
-        self.bits.get_bit(4)
+        self.bits & (1 << 4) != 0
     }
 
     /// Supervisor Timer Interrupt Enable
     #[inline]
     pub fn stimer(&self) -> bool {
-        self.bits.get_bit(5)
+        self.bits & (1 << 5) != 0
     }
 
     /// Machine Timer Interrupt Enable
     #[inline]
     pub fn mtimer(&self) -> bool {
-        self.bits.get_bit(7)
+        self.bits & (1 << 7) != 0
     }
 
     /// User External Interrupt Enable
     #[inline]
     pub fn uext(&self) -> bool {
-        self.bits.get_bit(8)
+        self.bits & (1 << 8) != 0
     }
 
     /// Supervisor External Interrupt Enable
     #[inline]
     pub fn sext(&self) -> bool {
-        self.bits.get_bit(9)
+        self.bits & (1 << 9) != 0
     }
 
     /// Machine External Interrupt Enable
     #[inline]
     pub fn mext(&self) -> bool {
-        self.bits.get_bit(11)
+        self.bits & (1 << 11) != 0
     }
 }