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Merge pull request #270 from hegza/pr/write-pcounters
riscv: make mcycle & minstret writable
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riscv/CHANGELOG.md

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@@ -7,6 +7,11 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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## [Unreleased]
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### Added
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- CSR helper macro `write_composite_csr` for writing 64-bit CSRs on 32-bit targets.
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- Write utilities for `mcycle`, `minstret`
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## [v0.13.0] - 2025-02-18
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### Added

riscv/src/register/macros.rs

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@@ -449,6 +449,30 @@ macro_rules! read_composite_csr {
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};
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}
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/// Convenience macro to write a composite value to a CSR register.
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///
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/// - `RV32`: writes 32-bits into `hi` and 32-bits into `lo` to create a 64-bit value
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/// - `RV64`: writes a 64-bit value into `lo`
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#[macro_export]
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macro_rules! write_composite_csr {
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($hi:expr, $lo:expr) => {
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/// Writes the CSR as a 64-bit value
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#[inline]
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pub unsafe fn write64(bits: u64) {
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match () {
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#[cfg(target_arch = "riscv32")]
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() => {
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$hi((bits >> 32) as usize);
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$lo(bits as usize);
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}
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#[cfg(not(target_arch = "riscv32"))]
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() => $lo(bits as usize),
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}
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}
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};
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}
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macro_rules! set_pmp {
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() => {
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/// Set the pmp configuration corresponding to the index.

riscv/src/register/mcycle.rs

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//! mcycle register
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read_csr_as_usize!(0xB00);
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write_csr_as_usize!(0xB00);
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read_composite_csr!(super::mcycleh::read(), read());
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write_composite_csr!(super::mcycleh::write, write);

riscv/src/register/mcycleh.rs

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//! mcycleh register
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read_csr_as_usize_rv32!(0xB80);
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write_csr_as_usize_rv32!(0xB80);

riscv/src/register/minstret.rs

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//! minstret register
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read_csr_as_usize!(0xB02);
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write_csr_as_usize!(0xB02);
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read_composite_csr!(super::minstreth::read(), read());
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write_composite_csr!(super::minstreth::write, write);

riscv/src/register/minstreth.rs

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//! minstreth register
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read_csr_as_usize_rv32!(0xB82);
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write_csr_as_usize_rv32!(0xB82);

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