Merge branch 'rust-embedded:master' into master

Author: dkhayes117

.github/bors.toml

@@ -1,4 +1,10 @@
 block_labels = ["needs-decision"]
 delete_merged_branches = true
 required_approvals = 1
-status = ["continuous-integration/travis-ci/push"]
+status = [
+    "ci-linux (stable)",
+    "ci-linux (1.42.0)",
+    "build-other (macOS-latest)",
+    "build-other (windows-latest)",
+    "Rustfmt"
+]

.github/workflows/ci.yaml

@@ -0,0 +1,61 @@
+on:
+  push:
+    branches: [ staging, trying, master ]
+  pull_request:
+
+name: Continuous integration
+
+jobs:
+  ci-linux:
+    runs-on: ubuntu-20.04
+    continue-on-error: ${{ matrix.experimental || false }}
+    strategy:
+      matrix:
+        # All generated code should be running on stable now, MRSV is 1.42.0
+        rust: [nightly, stable, 1.42.0]
+
+        include:
+          # Nightly is only for reference and allowed to fail
+          - rust: nightly
+            experimental: true
+
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: ${{ matrix.rust }}
+          override: true
+      - name: Install all Rust targets for ${{ matrix.rust }}
+        run: rustup target install --toolchain=${{ matrix.rust }} x86_64-unknown-linux-gnu riscv32imac-unknown-none-elf riscv64imac-unknown-none-elf riscv64gc-unknown-none-elf
+      - name: Install riscv gcc
+        run: sudo apt-get update && sudo apt-get install -y gcc-riscv64-unknown-elf
+      - name: Run CI script for x86_64-unknown-linux-gnu under ${{ matrix.rust }}
+        run: cargo check --target x86_64-unknown-linux-gnu
+      - name: Run CI script for riscv32imac-unknown-none-elf under ${{ matrix.rust }}
+        run: cargo check --target riscv32imac-unknown-none-elf
+      - name: Run CI script for riscv64imac-unknown-none-elf under ${{ matrix.rust }}
+        run: cargo check --target riscv64imac-unknown-none-elf
+      - name: Run CI script for riscv64gc-unknown-none-elf under ${{ matrix.rust }}
+        run: cargo check --target riscv64gc-unknown-none-elf
+      - name: Check blobs
+        run: ./check-blobs.sh
+
+  # On macOS and Windows, we at least make sure that the crate builds and links.
+  build-other:
+    strategy:
+      matrix:
+        os:
+          - macOS-latest
+          - windows-latest
+    runs-on: ${{ matrix.os }}
+
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+      - name: Build crate for host OS
+        run: cargo build

.github/workflows/rustfmt.yaml

@@ -0,0 +1,24 @@
+
+on:
+  push:
+    branches: [ staging, trying, master ]
+  pull_request:
+
+name: Code formatting check
+
+jobs:
+  fmt:
+    name: Rustfmt
+    runs-on: ubuntu-20.04
+    steps:
+      - uses: actions/checkout@v2
+      - uses: actions-rs/toolchain@v1
+        with:
+          profile: minimal
+          toolchain: stable
+          override: true
+          components: rustfmt
+      - uses: actions-rs/cargo@v1
+        with:
+          command: fmt
+          args: --all -- --check

.travis.yml

@@ -7,6 +7,23 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
 
 ## [Unreleased]
 
+## [v0.7.0] - 2020-07-29
+
+### Added
+
+- Add `medeleg` register
+- Add `cycle[h]`, `instret[h]` and `mcounteren`
+- Add additional binaries for floating-point ABIs
+- Add support for `mxr`
+- Add support for `mprv`
+
+### Changed
+
+- Fix `scause::set`
+- Various formatting and comment fixes
+- Update `bare-metal` to `v1.0.0` removing `Nr` trait
+- Build targets on `docs.rs` are now RISC-V targets other than default ones
+
 ## [v0.6.0] - 2020-06-20
 
 ### Changed

CHANGELOG.md

@@ -1,15 +1,22 @@
 [package]
 name = "riscv"
-version = "0.6.0"
+version = "0.7.0"
 repository = "https://github.com/rust-embedded/riscv"
 authors = ["The RISC-V Team <risc-v@teams.rust-embedded.org>"]
 categories = ["embedded", "hardware-support", "no-std"]
 description = "Low level access to RISC-V processors"
 keywords = ["riscv", "register", "peripheral"]
 license = "ISC"
 
+[package.metadata.docs.rs]
+default-target = "riscv64imac-unknown-none-elf"
+targets = [
+    "riscv32i-unknown-none-elf", "riscv32imc-unknown-none-elf", "riscv32imac-unknown-none-elf",
+    "riscv64imac-unknown-none-elf", "riscv64gc-unknown-none-elf",
+]
+
 [dependencies]
-bare-metal = "0.2.5"
+bare-metal = "1.0.0"
 bit_field = "0.10.0"
 
 [build-dependencies]

Cargo.toml

@@ -38,4 +38,4 @@ Conduct][CoC], the maintainer of this crate, the [RISC-V team][team], promises
 to intervene to uphold that code of conduct.
 
 [CoC]: CODE_OF_CONDUCT.md
-[team]: https://github.com/rust-embedded/wg#the-riscv-team
+[team]: https://github.com/rust-embedded/wg#the-risc-v-team

README.md

@@ -17,4 +17,28 @@ riscv64-unknown-elf-ar crs bin/riscv64i-unknown-none-elf.a bin/$crate.o
 riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64ic asm.S -o bin/$crate.o
 riscv64-unknown-elf-ar crs bin/riscv64ic-unknown-none-elf.a bin/$crate.o
 
+riscv64-unknown-elf-gcc -c -mabi=ilp32f -march=rv32if asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32if-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=ilp32f -march=rv32ifc asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32ifc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64f -march=rv64if asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64if-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64f -march=rv64ifc asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64ifc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=ilp32d -march=rv32ifd asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32ifd-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=ilp32d -march=rv32ifdc asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv32ifdc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64d -march=rv64ifd asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64ifd-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64d -march=rv64ifdc asm.S -o bin/$crate.o
+riscv64-unknown-elf-ar crs bin/riscv64ifdc-unknown-none-elf.a bin/$crate.o
+
 Remove-Item bin/$crate.o

assemble.ps1

@@ -19,4 +19,28 @@ ar crs bin/riscv64i-unknown-none-elf.a bin/$crate.o
 riscv64-unknown-elf-gcc -c -mabi=lp64 -march=rv64ic asm.S -o bin/$crate.o
 ar crs bin/riscv64ic-unknown-none-elf.a bin/$crate.o
 
+riscv64-unknown-elf-gcc -c -mabi=ilp32f -march=rv32if asm.S -o bin/$crate.o
+ar crs bin/riscv32if-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=ilp32f -march=rv32ifc asm.S -o bin/$crate.o
+ar crs bin/riscv32ifc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64f -march=rv64if asm.S -o bin/$crate.o
+ar crs bin/riscv64if-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64f -march=rv64ifc asm.S -o bin/$crate.o
+ar crs bin/riscv64ifc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=ilp32d -march=rv32ifd asm.S -o bin/$crate.o
+ar crs bin/riscv32ifd-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=ilp32d -march=rv32ifdc asm.S -o bin/$crate.o
+ar crs bin/riscv32ifdc-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64d -march=rv64ifd asm.S -o bin/$crate.o
+ar crs bin/riscv64ifd-unknown-none-elf.a bin/$crate.o
+
+riscv64-unknown-elf-gcc -c -mabi=lp64d -march=rv64ifdc asm.S -o bin/$crate.o
+ar crs bin/riscv64ifdc-unknown-none-elf.a bin/$crate.o
+
 rm bin/$crate.o