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scontext
1 parent 7a73715 commit 541c36fCopy full SHA for 541c36f
riscv/src/register/scontext.rs
@@ -27,3 +27,26 @@ read_write_csr_field! {
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/// Represents the `data` context number of the `scontext` CSR.
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data: [0:31],
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}
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+
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+#[cfg(test)]
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+mod tests {
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+ use super::*;
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+ #[test]
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+ fn test_scontext() {
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+ #[cfg(target_arch = "riscv32")]
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+ const DATA_BITS: usize = 16;
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+ #[cfg(not(target_arch = "riscv32"))]
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+ const DATA_BITS: usize = 32;
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+ let mut scontext = Scontext::from_bits(0);
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+ (1..=DATA_BITS)
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+ .map(|b| ((1u64 << b) - 1) as usize)
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+ .for_each(|data| {
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+ scontext.set_data(data);
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+ assert_eq!(scontext.data(), data);
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+ assert_eq!(scontext.bits(), data);
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+ });
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+ }
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+}
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