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bors[bot]Disasm
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Merge #95
95: Pass a0..a2 to main() r=almindor a=Disasm This PR delivers arguments stored in a0..a2 to `main`. Fixes rust-embedded/riscv-rt#92 Tested with: * build the `empty` example for `riscv64imac-unknown-none-elf` with a memory file which puts everything to `0x80000000` * run `qemu-system-riscv64 -nographic -machine virt -bios target/riscv64imac-unknown-none-elf/release/examples/empty -s -S` * connect to qemu with gdb (`target remote :1234`) * set breakpoint to main (`b main`) * resume execution (`continue`) * inspect registers (`info registers`) ``` a0 0x0 0 a1 0x87000000 2264924160 a2 0x1028 4136 ``` * check header (`x/xw 0x87000000`) ``` 0x87000000: 0xedfe0dd0 ``` Co-authored-by: Vadim Kaushan <admin@disasm.info>
2 parents 6bd66a2 + 57219ef commit 4b98bd4

29 files changed

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riscv-rt/Cargo.toml

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@@ -12,7 +12,7 @@ license = "ISC"
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[dependencies]
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r0 = "1.0.0"
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riscv = "0.8"
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riscv-rt-macros = { path = "macros", version = "0.1.6" }
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riscv-rt-macros = { path = "macros", version = "0.2.0" }
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[dev-dependencies]
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panic-halt = "0.2.0"

riscv-rt/asm.S

Lines changed: 8 additions & 10 deletions
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@@ -58,9 +58,7 @@ _abs_start:
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li x7, 0
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li x8, 0
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li x9, 0
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li x10,0
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li x11,0
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li x12,0
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// a0..a2 (x10..x12) skipped
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li x13,0
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li x14,0
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li x15,0
@@ -87,23 +85,23 @@ _abs_start:
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.option pop
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// Check hart id
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csrr a2, mhartid
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csrr t2, mhartid
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lui t0, %hi(_max_hart_id)
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add t0, t0, %lo(_max_hart_id)
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bgtu a2, t0, abort
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bgtu t2, t0, abort
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// Allocate stacks
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la sp, _stack_start
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lui t0, %hi(_hart_stack_size)
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add t0, t0, %lo(_hart_stack_size)
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#ifdef __riscv_mul
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mul t0, a2, t0
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mul t0, t2, t0
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#else
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beqz a2, 2f // Jump if single-hart
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mv t1, a2
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mv t2, t0
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beqz t2, 2f // Jump if single-hart
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mv t1, t2
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mv t3, t0
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1:
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add t0, t0, t2
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add t0, t0, t3
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addi t1, t1, -1
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bnez t1, 1b
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