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Merge pull request #220 from jasonwhite/jw/mstatus-vs
mstatus: Support vector extension
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riscv/CHANGELOG.md

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@@ -18,6 +18,7 @@ and this project adheres to [Semantic Versioning](http://semver.org/).
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- Export `riscv::register::macros` module macros for external use
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- Add `riscv::register::mcountinhibit` module for `mcountinhibit` CSR
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- Add `Mcounteren` in-memory update functions
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- Add `Mstatus` vector extension support
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### Fixed
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riscv/src/register/mstatus.rs

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@@ -41,6 +41,15 @@ pub enum FS {
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Dirty = 3,
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}
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/// Vector extension state
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#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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pub enum VS {
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Off = 0,
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Initial = 1,
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Clean = 2,
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Dirty = 3,
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}
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/// Machine Previous Privilege Mode
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#[derive(Copy, Clone, Debug, Eq, PartialEq)]
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pub enum MPP {
@@ -216,6 +225,19 @@ impl Mstatus {
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}
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}
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/// Vector extension state
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#[inline]
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pub fn vs(&self) -> VS {
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let fs = bf_extract(self.bits, 9, 2); // bits 9-10
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match fs {
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0b00 => VS::Off,
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0b01 => VS::Initial,
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0b10 => VS::Clean,
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0b11 => VS::Dirty,
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_ => unreachable!(),
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}
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}
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/// Update Floating-point extension state
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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self.bits = bf_insert(self.bits, 13, 2, fs as usize);
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}
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/// Update vector extension state
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///
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/// Note this updates a previously read [`Mstatus`] value, but does not
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/// affect the mstatus CSR itself. See [`set_vs`] to directly update the
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/// CSR.
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#[inline]
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pub fn set_vs(&mut self, vs: VS) {
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self.bits = bf_insert(self.bits, 9, 2, vs as usize);
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}
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/// Additional extension state
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///
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/// Encodes the status of additional user-mode extensions and associated
@@ -559,6 +591,15 @@ pub unsafe fn set_fs(fs: FS) {
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_write(value);
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}
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/// Vector extension state
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#[inline]
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pub unsafe fn set_vs(vs: VS) {
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let mut value = _read();
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value &= !(0x3 << 9); // clear previous value
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value |= (vs as usize) << 9;
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_write(value);
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}
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/// Set S-mode non-instruction-fetch memory endianness
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///
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/// # Note

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