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mtval2
1 parent 6c33cce commit 04b95cbCopy full SHA for 04b95cb
riscv/src/register/mtval2.rs
@@ -21,3 +21,22 @@ impl Mtval2 {
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self.bits() << Self::GUEST_PAGE_SHIFT
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}
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+
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+#[cfg(test)]
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+mod tests {
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+ use super::*;
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+ #[test]
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+ fn test_mtval2() {
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+ (1..=usize::BITS)
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+ .map(|r| ((1u128 << r) - 1) as usize)
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+ .for_each(|bits| {
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+ let mtval2 = Mtval2::from_bits(bits);
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+ assert_eq!(mtval2.bits(), bits);
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+ assert_eq!(
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+ mtval2.guest_fault_address(),
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+ bits << Mtval2::GUEST_PAGE_SHIFT
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+ );
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+ });
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+ }
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+}
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