Skip to content

Commit cdf6be7

Browse files
committed
New 07 Registers
Modified to run using `stm32f3-discovery` instead of `f3` and updated the `.md` files appropriately.
1 parent 6a791e0 commit cdf6be7

File tree

8 files changed

+342
-273
lines changed

8 files changed

+342
-273
lines changed

src/07-registers/Cargo.toml

Lines changed: 5 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,11 @@
11
[package]
2-
authors = ["Jorge Aparicio <jorge@japaric.io>"]
2+
authors = [
3+
"Jorge Aparicio <jorge@japaric.io>",
4+
"Wink Saville <wink@saville.com",
5+
]
36
edition = "2018"
47
name = "registers"
5-
version = "0.1.0"
8+
version = "0.2.0"
69

710
[dependencies]
811
aux7 = { path = "auxiliary" }

src/07-registers/auxiliary/Cargo.toml

Lines changed: 13 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,14 +1,19 @@
11
[package]
2-
authors = ["Jorge Aparicio <jorge@japaric.io>"]
2+
authors = [
3+
"Jorge Aparicio <jorge@japaric.io>",
4+
"Wink Saville <wink@saville.com",
5+
]
36
edition = "2018"
47
name = "aux7"
5-
version = "0.1.0"
8+
version = "0.2.0"
69

710
[dependencies]
8-
cortex-m = "0.6.3"
9-
cortex-m-rt = "0.6.3"
10-
panic-itm = "0.4.0"
11+
cortex-m = "0.6.4"
12+
cortex-m-rt = "0.6.13"
13+
stm32f3-discovery = "0.6.0"
14+
panic-halt = "0.2.0"
15+
panic-itm = "0.4.2"
1116

12-
[dependencies.f3]
13-
features = ["rt"]
14-
version = "0.6.1"
17+
[dependencies.stm32f3]
18+
version = "0.12.1"
19+
features = ["stm32f303", "rt"]

src/07-registers/auxiliary/src/lib.rs

Lines changed: 26 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -3,28 +3,38 @@
33
#![deny(warnings)]
44
#![no_std]
55

6-
#[allow(unused_extern_crates)] // NOTE(allow) bug rust-lang/rust#53964
76
extern crate panic_itm; // panic handler
87

98
pub use cortex_m::{asm::bkpt, iprint, iprintln, peripheral::ITM};
109
pub use cortex_m_rt::entry;
11-
use f3::{
12-
hal::{
13-
prelude::*,
14-
stm32f30x::gpioc,
15-
stm32f30x::{self, GPIOE},
16-
},
17-
led::Leds,
18-
};
1910

20-
#[inline(never)]
21-
pub fn init() -> (ITM, &'static gpioc::RegisterBlock) {
22-
let cp = cortex_m::Peripherals::take().unwrap();
23-
let dp = stm32f30x::Peripherals::take().unwrap();
11+
pub use stm32f3::stm32f303::{self, gpioc::RegisterBlock};
12+
pub use stm32f3_discovery::stm32f3xx_hal::pac::GPIOE;
13+
pub use stm32f3_discovery::{leds::Leds, stm32f3xx_hal};
14+
15+
use stm32f3xx_hal::prelude::*;
16+
pub use stm32f3xx_hal::stm32;
2417

25-
let mut rcc = dp.RCC.constrain();
18+
#[inline(never)]
19+
pub fn init() -> (ITM, &'static RegisterBlock) {
20+
let device_periphs = stm32::Peripherals::take().unwrap();
21+
let mut reset_and_clock_control = device_periphs.RCC.constrain();
2622

27-
Leds::new(dp.GPIOE.split(&mut rcc.ahb));
23+
// initialize user leds
24+
let mut gpioe = device_periphs.GPIOE.split(&mut reset_and_clock_control.ahb);
25+
let _leds = Leds::new(
26+
gpioe.pe8,
27+
gpioe.pe9,
28+
gpioe.pe10,
29+
gpioe.pe11,
30+
gpioe.pe12,
31+
gpioe.pe13,
32+
gpioe.pe14,
33+
gpioe.pe15,
34+
&mut gpioe.moder,
35+
&mut gpioe.otyper,
36+
);
2837

29-
(cp.ITM, unsafe { &*GPIOE::ptr() })
38+
let core_periphs = cortex_m::Peripherals::take().unwrap();
39+
(core_periphs.ITM, unsafe { &*stm32f303::GPIOE::ptr() })
3040
}

src/07-registers/bad-address.md

Lines changed: 44 additions & 38 deletions
Original file line numberDiff line numberDiff line change
@@ -29,16 +29,20 @@ Invalid in the sense that there's no register at this address.
2929
Now, let's try it.
3030

3131
``` console
32+
cargo run
3233
$ cargo run
33-
Breakpoint 3, main () at src/07-registers/src/main.rs:9
34-
9 aux7::init();
34+
(..)
35+
Breakpoint 1, registers::__cortex_m_rt_main_trampoline () at src/07-registers/src/main.rs:9
36+
9 #[entry]
3537

3638
(gdb) continue
3739
Continuing.
3840

39-
Breakpoint 2, cortex_m_rt::HardFault_ (ef=0x10001fb0)
40-
at $REGISTRY/cortex-m-rt-0.6.13/src/lib.rs:560
41+
Breakpoint 3, cortex_m_rt::HardFault_ (ef=0x20009fb0)
42+
at /home/wink/.cargo/registry/src/github.com-1ecc6299db9ec823/cortex-m-rt-0.6.13/src/lib.rs:560
4143
560 loop {
44+
45+
(gdb)
4246
```
4347

4448
We tried to do an invalid operation, reading memory that doesn't exist, so the processor raised an
@@ -77,13 +81,13 @@ We can get more information about the exception from the debugger. Let's see:
7781
(gdb) print/x *ef
7882
$1 = cortex_m_rt::ExceptionFrame {
7983
r0: 0x48001800,
80-
r1: 0x48001800,
81-
r2: 0xb,
82-
r3: 0xc,
83-
r12: 0xd,
84-
lr: 0x800019f,
85-
pc: 0x80028d6,
86-
xpsr: 0x1000000
84+
r1: 0x80036b0,
85+
r2: 0x1,
86+
r3: 0x80000000,
87+
r12: 0xb,
88+
lr: 0x800020d,
89+
pc: 0x8001750,
90+
xpsr: 0xa1000200
8791
}
8892
```
8993

@@ -93,25 +97,27 @@ disassemble the program around the bad instruction.
9397

9498
```
9599
(gdb) disassemble /m ef.pc
96-
Dump of assembler code for function core::ptr::read_volatile:
97-
471 /checkout/src/libcore/ptr.rs: No such file or directory.
98-
0x080028ce <+0>: sub sp, #16
99-
0x080028d0 <+2>: mov r1, r0
100-
0x080028d2 <+4>: str r0, [sp, #8]
101-
102-
472 in /checkout/src/libcore/ptr.rs
103-
0x080028d4 <+6>: ldr r0, [sp, #8]
104-
0x080028d6 <+8>: ldr r0, [r0, #0]
105-
0x080028d8 <+10>: str r0, [sp, #12]
106-
0x080028da <+12>: ldr r0, [sp, #12]
107-
0x080028dc <+14>: str r1, [sp, #4]
108-
0x080028de <+16>: str r0, [sp, #0]
109-
0x080028e0 <+18>: b.n 0x80028e2 <core::ptr::read_volatile+20>
110-
111-
473 in /checkout/src/libcore/ptr.rs
112-
0x080028e2 <+20>: ldr r0, [sp, #0]
113-
0x080028e4 <+22>: add sp, #16
114-
0x080028e6 <+24>: bx lr
100+
Dump of assembler code for function core::ptr::read_volatile<u32>:
101+
1046 pub unsafe fn read_volatile<T>(src: *const T) -> T {
102+
0x0800174c <+0>: sub sp, #12
103+
0x0800174e <+2>: str r0, [sp, #4]
104+
105+
1047 if cfg!(debug_assertions) && !is_aligned_and_not_null(src) {
106+
1048 // Not panicking to keep codegen impact smaller.
107+
1049 abort();
108+
1050 }
109+
1051 // SAFETY: the caller must uphold the safety contract for `volatile_load`.
110+
1052 unsafe { intrinsics::volatile_load(src) }
111+
0x08001750 <+4>: ldr r0, [r0, #0]
112+
0x08001752 <+6>: str r0, [sp, #8]
113+
0x08001754 <+8>: ldr r0, [sp, #8]
114+
0x08001756 <+10>: str r0, [sp, #0]
115+
0x08001758 <+12>: b.n 0x800175a <core::ptr::read_volatile<u32>+14>
116+
117+
1053 }
118+
0x0800175a <+14>: ldr r0, [sp, #0]
119+
0x0800175c <+16>: add sp, #12
120+
0x0800175e <+18>: bx lr
115121
116122
End of assembler dump.
117123
```
@@ -126,16 +132,16 @@ when the exception was raised? Well, we already did! The `r0` field in the `ef`
126132
before is the value of `r0` register had when the exception was raised. Here it is again:
127133

128134
```
129-
(gdb) p/x *ef
135+
(gdb) print/x *ef
130136
$1 = cortex_m_rt::ExceptionFrame {
131137
r0: 0x48001800,
132-
r1: 0x48001800,
133-
r2: 0xb,
134-
r3: 0xc,
135-
r12: 0xd,
136-
lr: 0x800019f,
137-
pc: 0x80028d6,
138-
xpsr: 0x1000000
138+
r1: 0x80036b0,
139+
r2: 0x1,
140+
r3: 0x80000000,
141+
r12: 0xb,
142+
lr: 0x800020d,
143+
pc: 0x8001750,
144+
xpsr: 0xa1000200
139145
}
140146
```
141147

src/07-registers/openocd.gdb

Lines changed: 2 additions & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -1,10 +1,11 @@
11
target remote :3333
22
set print asm-demangle on
33
set print pretty on
4+
set style sources off
45
monitor tpiu config internal itm.txt uart off 8000000
56
monitor itm port 0 on
67
load
8+
break main
79
break DefaultHandler
810
break HardFault
9-
break main
1011
continue

0 commit comments

Comments
 (0)