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Define the CCSIDR_EL1 register
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src/registers.rs

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#[macro_use]
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mod macros;
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mod ccsidr_el1;
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mod clidr_el1;
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mod cntfrq_el0;
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mod cnthctl_el2;
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mod vbar_el1;
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mod vbar_el2;
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pub use ccsidr_el1::{CCSIDR_EL1, CSSIDR_EL1_WITH_FEAT_CCIDX};
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pub use clidr_el1::CLIDR_EL1;
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pub use cntfrq_el0::CNTFRQ_EL0;
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pub use cnthctl_el2::CNTHCTL_EL2;

src/registers/ccsidr_el1.rs

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// SPDX-License-Identifier: Apache-2.0 OR MIT
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//
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// Copyright (c) 2018-2022 by the author(s)
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//
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// Author(s):
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// - Valentin B. <valentin.be@protonmail.com>
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//! Current Cache Size ID Register - EL1
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//!
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//! Provides information about the architecture of the currently selected cache.
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use tock_registers::{
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interfaces::{Readable, Writeable},
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register_bitfields,
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};
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register_bitfields! {u64,
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/// The representation of `CCSIDR_EL1` when `FEAT_CCIDX` is implemented.
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pub CCSIDR_EL1_WITH_FEAT_CCIDX [
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/// Number of sets in cache.
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///
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/// A value of 0 indicates 1 set in the cache. The number does not
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/// necessarily have to be a power of 2.
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NumSets OFFSET(32) NUMBITS(24) [],
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/// Associativity of cache.
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///
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/// A value of 0 indicates an associativity of 1. The value does not
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/// necessarily have to be a power of 2.
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Associativity OFFSET(3) NUMBITS(21) [],
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/// Log2(Number of bytes in cache lline) - 4.
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///
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/// **Examples:**
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///
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/// - For a line length of 16 bytes: Log2(16) - 4 = 0. This is the minimum line length.
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///
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/// - For a line length of 32 bytes: Log2(32) - 4 = 1.
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LineSize OFFSET(0) NUMBITS(3) []
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],
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/// The representation of `CCSIDR_EL1` otherwise.
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pub CCSIDR_EL1 [
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/// Number of sets in cache.
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///
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/// A value of 0 indicates 1 set in the cache. The number does not
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/// necessarily have to be a power of 2.
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NumSets OFFSET(13) NUMBITS(15) [],
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/// Associativity of cache.
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///
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/// A value of 0 indicates an associativity of 1. The value does not
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/// necessarily have to be a power of 2.
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Associativity OFFSET(3) NUMBITS(10) [],
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/// Log2(Number of bytes in cache lline) - 4.
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///
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/// **Examples:**
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///
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/// - For a line length of 16 bytes: Log2(16) - 4 = 0. This is the minimum line length.
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///
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/// - For a line length of 32 bytes: Log2(32) - 4 = 1.
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LineSize OFFSET(0) NUMBITS(3) []
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]
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}
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pub struct RegWithFeatCcidx;
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pub struct Reg;
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impl Readable for RegWithFeatCcidx {
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type T = u64;
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type R = CCSIDR_EL1_WITH_FEAT_CCIDX::Register;
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sys_coproc_read_raw!(u64, "CCSIDR_EL1", "x");
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}
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impl Writeable for RegWithFeatCcidx {
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type T = u64;
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type R = CCSIDR_EL1_WITH_FEAT_CCIDX::Register;
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sys_coproc_write_raw!(u64, "CCSIDR_EL1", "x");
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}
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impl Readable for Reg {
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type T = u64;
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type R = CCSIDR_EL1::Register;
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sys_coproc_read_raw!(u64, "CCSIDR_EL1", "x");
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}
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impl Writeable for Reg {
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type T = u64;
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type R = CCSIDR_EL1::Register;
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sys_coproc_write_raw!(u64, "CCSIDR_EL1", "x");
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}
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pub const CCSIDR_EL1_WITH_FEAT_CCIDX: RegWithFeatCcidx = RegWithFeatCcidx;
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pub const CCSIDR_EL1: Reg = Reg;

src/registers/csselr_el1.rs

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// Author(s):
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// - Valentin B. <valentin.be@protonmail.com>
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//! Current Cache Size ID Register - EL1
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//! Cache Size Selection Register - EL1
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//!
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//! Provides information about the architecture of the currently selected cache.
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//! Selects the current Cache Size ID Register, CCSIDR_EL1, by specifying the
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//! required cache level and the cache type (either instruction or data cache).
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use tock_registers::{
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interfaces::{Readable, Writeable},

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