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13 files changed

+361
-255
lines changed

13 files changed

+361
-255
lines changed

src/bus.rs

Lines changed: 28 additions & 23 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1+
use crate::endpoint::{Endpoint, EndpointAddress, EndpointDirection, EndpointType};
2+
use crate::{Result, UsbDirection, UsbError};
13
use core::cell::RefCell;
2-
use core::sync::atomic::{AtomicPtr, Ordering};
34
use core::mem;
45
use core::ptr;
5-
use crate::{Result, UsbDirection, UsbError};
6-
use crate::endpoint::{Endpoint, EndpointDirection, EndpointType, EndpointAddress};
6+
use core::sync::atomic::{AtomicPtr, Ordering};
77

88
/// A trait for device-specific USB peripherals. Implement this to add support for a new hardware
99
/// platform.
@@ -41,7 +41,8 @@ pub trait UsbBus: Sync + Sized {
4141
ep_addr: Option<EndpointAddress>,
4242
ep_type: EndpointType,
4343
max_packet_size: u16,
44-
interval: u8) -> Result<EndpointAddress>;
44+
interval: u8,
45+
) -> Result<EndpointAddress>;
4546

4647
/// Enables and initializes the USB peripheral. Soon after enabling the device will be reset, so
4748
/// there is no need to perform a USB reset in this method.
@@ -215,14 +216,11 @@ impl<B: UsbBus> UsbBusAllocator<B> {
215216
ep_addr: Option<EndpointAddress>,
216217
ep_type: EndpointType,
217218
max_packet_size: u16,
218-
interval: u8) -> Result<Endpoint<'_, B, D>>
219-
{
220-
self.bus.borrow_mut()
221-
.alloc_ep(
222-
D::DIRECTION,
223-
ep_addr, ep_type,
224-
max_packet_size,
225-
interval)
219+
interval: u8,
220+
) -> Result<Endpoint<'_, B, D>> {
221+
self.bus
222+
.borrow_mut()
223+
.alloc_ep(D::DIRECTION, ep_addr, ep_type, max_packet_size, interval)
226224
.map(|a| Endpoint::new(&self.bus_ptr, a, ep_type, max_packet_size, interval))
227225
}
228226

@@ -242,7 +240,8 @@ impl<B: UsbBus> UsbBusAllocator<B> {
242240
/// feasibly recoverable.
243241
#[inline]
244242
pub fn control<D: EndpointDirection>(&self, max_packet_size: u16) -> Endpoint<'_, B, D> {
245-
self.alloc(None, EndpointType::Control, max_packet_size, 0).expect("alloc_ep failed")
243+
self.alloc(None, EndpointType::Control, max_packet_size, 0)
244+
.expect("alloc_ep failed")
246245
}
247246

248247
/// Allocates a bulk endpoint.
@@ -257,7 +256,8 @@ impl<B: UsbBus> UsbBusAllocator<B> {
257256
/// feasibly recoverable.
258257
#[inline]
259258
pub fn bulk<D: EndpointDirection>(&self, max_packet_size: u16) -> Endpoint<'_, B, D> {
260-
self.alloc(None, EndpointType::Bulk, max_packet_size, 0).expect("alloc_ep failed")
259+
self.alloc(None, EndpointType::Bulk, max_packet_size, 0)
260+
.expect("alloc_ep failed")
261261
}
262262

263263
/// Allocates an interrupt endpoint.
@@ -269,11 +269,12 @@ impl<B: UsbBus> UsbBusAllocator<B> {
269269
/// Panics if endpoint allocation fails, because running out of endpoints or memory is not
270270
/// feasibly recoverable.
271271
#[inline]
272-
pub fn interrupt<D: EndpointDirection>(&self, max_packet_size: u16, interval: u8)
273-
-> Endpoint<'_, B, D>
274-
{
275-
self
276-
.alloc(None, EndpointType::Interrupt, max_packet_size, interval)
272+
pub fn interrupt<D: EndpointDirection>(
273+
&self,
274+
max_packet_size: u16,
275+
interval: u8,
276+
) -> Endpoint<'_, B, D> {
277+
self.alloc(None, EndpointType::Interrupt, max_packet_size, interval)
277278
.expect("alloc_ep failed")
278279
}
279280
}
@@ -283,7 +284,9 @@ impl<B: UsbBus> UsbBusAllocator<B> {
283284
pub struct InterfaceNumber(u8);
284285

285286
impl From<InterfaceNumber> for u8 {
286-
fn from(n: InterfaceNumber) -> u8 { n.0 }
287+
fn from(n: InterfaceNumber) -> u8 {
288+
n.0
289+
}
287290
}
288291

289292
/// A handle for a USB string descriptor that contains its index.
@@ -297,7 +300,9 @@ impl StringIndex {
297300
}
298301

299302
impl From<StringIndex> for u8 {
300-
fn from(i: StringIndex) -> u8 { i.0 }
303+
fn from(i: StringIndex) -> u8 {
304+
i.0
305+
}
301306
}
302307

303308
/// Event and incoming packet information returned by [`UsbBus::poll`].
@@ -322,7 +327,7 @@ pub enum PollResult {
322327

323328
/// A SETUP packet has been received. This event should continue to be reported until the
324329
/// packet is read. The corresponding bit in `ep_out` may also be set but is ignored.
325-
ep_setup: u16
330+
ep_setup: u16,
326331
},
327332

328333
/// A USB suspend request has been detected or, in the case of self-powered devices, the device
@@ -332,4 +337,4 @@ pub enum PollResult {
332337
/// A USB resume request has been detected after being suspended or, in the case of self-powered
333338
/// devices, the device has been connected to the USB bus.
334339
Resume,
335-
}
340+
}

src/class.rs

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -1,9 +1,9 @@
1-
use crate::{Result, UsbError};
2-
use crate::bus::{UsbBus, StringIndex};
3-
use crate::descriptor::{DescriptorWriter, BosWriter};
1+
use crate::bus::{StringIndex, UsbBus};
42
use crate::control;
53
use crate::control_pipe::ControlPipe;
4+
use crate::descriptor::{BosWriter, DescriptorWriter};
65
use crate::endpoint::EndpointAddress;
6+
use crate::{Result, UsbError};
77

88
/// A trait for implementing USB classes.
99
///
@@ -21,7 +21,7 @@ pub trait UsbClass<B: UsbBus> {
2121
/// using `?`.
2222
fn get_configuration_descriptors(&self, writer: &mut DescriptorWriter) -> Result<()> {
2323
let _ = writer;
24-
Ok (())
24+
Ok(())
2525
}
2626

2727
/// Called when a GET_DESCRIPTOR request is received for a BOS descriptor.
@@ -30,7 +30,7 @@ pub trait UsbClass<B: UsbBus> {
3030
/// [UsbDevice](crate::device::UsbDevice) and shouldn't be written by classes.
3131
fn get_bos_descriptors(&self, writer: &mut BosWriter) -> Result<()> {
3232
let _ = writer;
33-
Ok (())
33+
Ok(())
3434
}
3535

3636
/// Gets a class-specific string descriptor.
@@ -49,10 +49,10 @@ pub trait UsbClass<B: UsbBus> {
4949
}
5050

5151
/// Called after a USB reset after the bus reset sequence is complete.
52-
fn reset(&mut self) { }
52+
fn reset(&mut self) {}
5353

5454
/// Called whenever the `UsbDevice` is polled.
55-
fn poll(&mut self) { }
55+
fn poll(&mut self) {}
5656

5757
/// Called when a control request is received with direction HostToDevice.
5858
///
@@ -126,7 +126,7 @@ pub struct ControlIn<'a, 'p, 'r, B: UsbBus> {
126126
req: &'r control::Request,
127127
}
128128

129-
impl<'a, 'p, 'r, B: UsbBus> ControlIn<'a, 'p, 'r, B> {
129+
impl<'a, 'p, 'r, B: UsbBus> ControlIn<'a, 'p, 'r, B> {
130130
pub(crate) fn new(pipe: &'p mut ControlPipe<'a, B>, req: &'r control::Request) -> Self {
131131
ControlIn { pipe, req }
132132
}

src/control.rs

Lines changed: 5 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -105,9 +105,11 @@ impl Request {
105105
Ok(Request {
106106
direction: rt.into(),
107107
request_type: unsafe { mem::transmute((rt >> 5) & 0b11) },
108-
recipient:
109-
if recipient <= 3 { unsafe { mem::transmute(recipient) } }
110-
else { Recipient::Reserved },
108+
recipient: if recipient <= 3 {
109+
unsafe { mem::transmute(recipient) }
110+
} else {
111+
Recipient::Reserved
112+
},
111113
request: buf[1],
112114
value: (buf[2] as u16) | ((buf[3] as u16) << 8),
113115
index: (buf[4] as u16) | ((buf[5] as u16) << 8),

src/control_pipe.rs

Lines changed: 16 additions & 16 deletions
Original file line numberDiff line numberDiff line change
@@ -1,8 +1,8 @@
1-
use core::cmp::min;
2-
use crate::{Result, UsbDirection, UsbError};
31
use crate::bus::UsbBus;
42
use crate::control::Request;
53
use crate::endpoint::{EndpointIn, EndpointOut};
4+
use crate::{Result, UsbDirection, UsbError};
5+
use core::cmp::min;
66

77
#[derive(Debug)]
88
#[allow(unused)]
@@ -81,17 +81,17 @@ impl<B: UsbBus> ControlPipe<'_, B> {
8181
// Failed to parse SETUP packet
8282
self.set_error();
8383
return None;
84-
},
84+
}
8585
};
8686

8787
// Now that we have properly parsed the setup packet, ensure the end-point is no longer in
8888
// a stalled state.
8989
self.ep_out.unstall();
9090

9191
/*sprintln!("SETUP {:?} {:?} {:?} req:{} val:{} idx:{} len:{} {:?}",
92-
req.direction, req.request_type, req.recipient,
93-
req.request, req.value, req.index, req.length,
94-
self.state);*/
92+
req.direction, req.request_type, req.recipient,
93+
req.request, req.value, req.index, req.length,
94+
self.state);*/
9595

9696
if req.direction == UsbDirection::Out {
9797
// OUT transfer
@@ -137,7 +137,7 @@ impl<B: UsbBus> ControlPipe<'_, B> {
137137
// sends more data than it indicated in the SETUP request)
138138
self.set_error();
139139
return None;
140-
},
140+
}
141141
};
142142

143143
self.i += count;
@@ -146,18 +146,18 @@ impl<B: UsbBus> ControlPipe<'_, B> {
146146
self.state = ControlState::CompleteOut;
147147
return Some(req);
148148
}
149-
},
149+
}
150150
ControlState::StatusOut => {
151151
self.ep_out.read(&mut []).ok();
152152
self.state = ControlState::Idle;
153-
},
153+
}
154154
_ => {
155155
// Discard the packet
156156
self.ep_out.read(&mut []).ok();
157157

158158
// Unexpected OUT packet
159159
self.set_error()
160-
},
160+
}
161161
}
162162

163163
return None;
@@ -167,7 +167,7 @@ impl<B: UsbBus> ControlPipe<'_, B> {
167167
match self.state {
168168
ControlState::DataIn => {
169169
self.write_in_chunk();
170-
},
170+
}
171171
ControlState::DataInZlp => {
172172
if self.ep_in.write(&[]).is_err() {
173173
// There isn't much we can do if the write fails, except to wait for another
@@ -176,15 +176,15 @@ impl<B: UsbBus> ControlPipe<'_, B> {
176176
}
177177

178178
self.state = ControlState::DataInLast;
179-
},
179+
}
180180
ControlState::DataInLast => {
181181
self.ep_out.unstall();
182182
self.state = ControlState::StatusOut;
183-
},
183+
}
184184
ControlState::StatusIn => {
185185
self.state = ControlState::Idle;
186186
return true;
187-
},
187+
}
188188
_ => {
189189
// Unexpected IN packet
190190
self.set_error();
@@ -198,7 +198,7 @@ impl<B: UsbBus> ControlPipe<'_, B> {
198198
let count = min(self.len - self.i, self.ep_in.max_packet_size() as usize);
199199

200200
let buffer = self.static_in_buf.unwrap_or(&self.buf);
201-
let count = match self.ep_in.write(&buffer[self.i..(self.i+count)]) {
201+
let count = match self.ep_in.write(&buffer[self.i..(self.i + count)]) {
202202
Ok(c) => c,
203203
// There isn't much we can do if the write fails, except to wait for another poll or for
204204
// the host to resend the request.
@@ -220,7 +220,7 @@ impl<B: UsbBus> ControlPipe<'_, B> {
220220

221221
pub fn accept_out(&mut self) -> Result<()> {
222222
match self.state {
223-
ControlState::CompleteOut => {},
223+
ControlState::CompleteOut => {}
224224
_ => return Err(UsbError::InvalidState),
225225
};
226226

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