fix: VAESDF assembly needs a spc(), not sep() (#998)

ThinkOpenly · web-flow · commit fd99207399f5 · 2025-06-01T17:02:23.000Z
Between the mnemonic and the operands, `sep()` (comma) was used instead
of `spc()` (space). Fix that.
diff --git a/model/riscv_insts_zvkned.sail b/model/riscv_insts_zvkned.sail
@@ -58,7 +58,7 @@ mapping vaesdf_mnemonic : zvk_vaesdf_funct6 <-> string = {
 }
 
 mapping clause assembly = VAESDF(funct6, vs2, vd)
-  <-> vaesdf_mnemonic(funct6) ^ sep() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2)
+  <-> vaesdf_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2)
 
 union clause ast = VAESDM : (zvk_vaesdm_funct6, vregidx, vregidx)
 

Original file line number	Diff line number	Diff line change
`@@ -58,7 +58,7 @@ mapping vaesdf_mnemonic : zvk_vaesdf_funct6 <-> string = {`
`58`	`58`	`}`
`59`	`59`
`60`	`60`	`mapping clause assembly = VAESDF(funct6, vs2, vd)`
`61`		`- <-> vaesdf_mnemonic(funct6) ^ sep() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2)`
	`61`	`+ <-> vaesdf_mnemonic(funct6) ^ spc() ^ vreg_name(vd) ^ sep() ^ vreg_name(vs2)`
`62`	`62`
`63`	`63`	`union clause ast = VAESDM : (zvk_vaesdm_funct6, vregidx, vregidx)`
`64`	`64`