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Remove redundant RISCV_ prefixes on internal ast nodes and enums
Pretty straightforward cleanup.
1 parent ed8c1a1 commit 5872942

16 files changed

+448
-456
lines changed

model/riscv_insts_base.sail

Lines changed: 116 additions & 116 deletions
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model/riscv_insts_zba.sail

Lines changed: 25 additions & 25 deletions
Original file line numberDiff line numberDiff line change
@@ -10,16 +10,16 @@ function clause currentlyEnabled(Ext_B) = hartSupports(Ext_B) & misa[B] == 0b1
1010
function clause currentlyEnabled(Ext_Zba) = hartSupports(Ext_Zba) | currentlyEnabled(Ext_B)
1111

1212
/* ****************************************************************** */
13-
union clause ast = RISCV_SLLIUW : (bits(6), regidx, regidx)
13+
union clause ast = SLLIUW : (bits(6), regidx, regidx)
1414

15-
mapping clause encdec = RISCV_SLLIUW(shamt, rs1, rd)
15+
mapping clause encdec = SLLIUW(shamt, rs1, rd)
1616
<-> 0b000010 @ shamt @ encdec_reg(rs1) @ 0b001 @ encdec_reg(rd) @ 0b0011011
1717
when currentlyEnabled(Ext_Zba) & xlen == 64
1818

19-
mapping clause assembly = RISCV_SLLIUW(shamt, rs1, rd)
19+
mapping clause assembly = SLLIUW(shamt, rs1, rd)
2020
<-> "slli.uw" ^ spc() ^ reg_name(rd) ^ sep() ^ reg_name(rs1) ^ sep() ^ hex_bits_6(shamt)
2121

22-
function clause execute (RISCV_SLLIUW(shamt, rs1, rd)) = {
22+
function clause execute (SLLIUW(shamt, rs1, rd)) = {
2323
let rs1_val = X(rs1);
2424
let result : xlenbits = zero_extend(rs1_val[31..0]) << shamt;
2525
X(rd) = result;
@@ -29,27 +29,27 @@ function clause execute (RISCV_SLLIUW(shamt, rs1, rd)) = {
2929
/* ****************************************************************** */
3030
union clause ast = ZBA_RTYPEUW : (regidx, regidx, regidx, bropw_zba)
3131

32-
mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, RISCV_ADDUW)
32+
mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, ADDUW)
3333
<-> 0b0000100 @ encdec_reg(rs2) @ encdec_reg(rs1) @ 0b000 @ encdec_reg(rd) @ 0b0111011
3434
when currentlyEnabled(Ext_Zba) & xlen == 64
3535

36-
mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, RISCV_SH1ADDUW)
36+
mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, SH1ADDUW)
3737
<-> 0b0010000 @ encdec_reg(rs2) @ encdec_reg(rs1) @ 0b010 @ encdec_reg(rd) @ 0b0111011
3838
when currentlyEnabled(Ext_Zba) & xlen == 64
3939

40-
mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, RISCV_SH2ADDUW)
40+
mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, SH2ADDUW)
4141
<-> 0b0010000 @ encdec_reg(rs2) @ encdec_reg(rs1) @ 0b100 @ encdec_reg(rd) @ 0b0111011
4242
when currentlyEnabled(Ext_Zba) & xlen == 64
4343

44-
mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, RISCV_SH3ADDUW)
44+
mapping clause encdec = ZBA_RTYPEUW(rs2, rs1, rd, SH3ADDUW)
4545
<-> 0b0010000 @ encdec_reg(rs2) @ encdec_reg(rs1) @ 0b110 @ encdec_reg(rd) @ 0b0111011
4646
when currentlyEnabled(Ext_Zba) & xlen == 64
4747

4848
mapping zba_rtypeuw_mnemonic : bropw_zba <-> string = {
49-
RISCV_ADDUW <-> "add.uw",
50-
RISCV_SH1ADDUW <-> "sh1add.uw",
51-
RISCV_SH2ADDUW <-> "sh2add.uw",
52-
RISCV_SH3ADDUW <-> "sh3add.uw"
49+
ADDUW <-> "add.uw",
50+
SH1ADDUW <-> "sh1add.uw",
51+
SH2ADDUW <-> "sh2add.uw",
52+
SH3ADDUW <-> "sh3add.uw"
5353
}
5454

5555
mapping clause assembly = ZBA_RTYPEUW(rs2, rs1, rd, op)
@@ -59,10 +59,10 @@ function clause execute (ZBA_RTYPEUW(rs2, rs1, rd, op)) = {
5959
let rs1_val = X(rs1);
6060
let rs2_val = X(rs2);
6161
let shamt : bits(2) = match op {
62-
RISCV_ADDUW => 0b00,
63-
RISCV_SH1ADDUW => 0b01,
64-
RISCV_SH2ADDUW => 0b10,
65-
RISCV_SH3ADDUW => 0b11
62+
ADDUW => 0b00,
63+
SH1ADDUW => 0b01,
64+
SH2ADDUW => 0b10,
65+
SH3ADDUW => 0b11
6666
};
6767
let result : xlenbits = (zero_extend(rs1_val[31..0]) << shamt) + rs2_val;
6868
X(rd) = result;
@@ -72,20 +72,20 @@ function clause execute (ZBA_RTYPEUW(rs2, rs1, rd, op)) = {
7272
/* ****************************************************************** */
7373
union clause ast = ZBA_RTYPE : (regidx, regidx, regidx, brop_zba)
7474

75-
mapping clause encdec = ZBA_RTYPE(rs2, rs1, rd, RISCV_SH1ADD)
75+
mapping clause encdec = ZBA_RTYPE(rs2, rs1, rd, SH1ADD)
7676
<-> 0b0010000 @ encdec_reg(rs2) @ encdec_reg(rs1) @ 0b010 @ encdec_reg(rd) @ 0b0110011
7777
when currentlyEnabled(Ext_Zba)
78-
mapping clause encdec = ZBA_RTYPE(rs2, rs1, rd, RISCV_SH2ADD)
78+
mapping clause encdec = ZBA_RTYPE(rs2, rs1, rd, SH2ADD)
7979
<-> 0b0010000 @ encdec_reg(rs2) @ encdec_reg(rs1) @ 0b100 @ encdec_reg(rd) @ 0b0110011
8080
when currentlyEnabled(Ext_Zba)
81-
mapping clause encdec = ZBA_RTYPE(rs2, rs1, rd, RISCV_SH3ADD)
81+
mapping clause encdec = ZBA_RTYPE(rs2, rs1, rd, SH3ADD)
8282
<-> 0b0010000 @ encdec_reg(rs2) @ encdec_reg(rs1) @ 0b110 @ encdec_reg(rd) @ 0b0110011
8383
when currentlyEnabled(Ext_Zba)
8484

8585
mapping zba_rtype_mnemonic : brop_zba <-> string = {
86-
RISCV_SH1ADD <-> "sh1add",
87-
RISCV_SH2ADD <-> "sh2add",
88-
RISCV_SH3ADD <-> "sh3add"
86+
SH1ADD <-> "sh1add",
87+
SH2ADD <-> "sh2add",
88+
SH3ADD <-> "sh3add"
8989
}
9090

9191
mapping clause assembly = ZBA_RTYPE(rs2, rs1, rd, op)
@@ -95,9 +95,9 @@ function clause execute (ZBA_RTYPE(rs2, rs1, rd, op)) = {
9595
let rs1_val = X(rs1);
9696
let rs2_val = X(rs2);
9797
let shamt : bits(2) = match op {
98-
RISCV_SH1ADD => 0b01,
99-
RISCV_SH2ADD => 0b10,
100-
RISCV_SH3ADD => 0b11
98+
SH1ADD => 0b01,
99+
SH2ADD => 0b10,
100+
SH3ADD => 0b11
101101
};
102102
let result : xlenbits = (rs1_val << shamt) + rs2_val;
103103
X(rd) = result;

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