Possibly Smivt, Ssivt simplification #621
Description
The space of major and local interrupt IDs is quite sparsely populated; when minor interrupts are vectored that leaves 3 possible major M-mode interrupt sources in a simple system : timer, software, and counter overflow.
These would make for a sparsely populated vector table, and little saving from vectoring especially as SW can easily use the contents of mtopi to index into a vector table if desired. The main argument for allowing these interrupts to be vectored is that if not vectored and not preemptible, worst-case interrupt latency would increase.
However it is still advantageous to have a major-interrupt handler address CSR that is distinct from the synchronous exception handler address.
There are some other possibilities -
- Since Interrupt ID 0 is reserved, let mtvec specify the base address of the major interrupts' vector table, with entry 0 containing the address of the handler for synchronous traps.
- Let mtvec point to the base address of a 2x XLEN sized block of memory, with the first word containing the address of the synchronous exception handler, and the address of the major interrupt handler in the second word.