It's unclear how `mhselect[2]` is concatenated with `mhvalue`

[en-sc]

[5.7.17. Trigger Extra (RV32) (textra32, at 0x7a3), mhselect filed description] states:

riscv-debug-spec/xml/hwbp_registers.xml

Lines 1446 to 1448 in 22a7576

	1, 5 (mcontext_select): This trigger will only match or fire if the
	low bits of
	{csr-mcontext}/{csr-hcontext} equal {{textra32-mhvalue}, mhselect[2]}.

It's unclear whether mhselect[2] is compared with the most significant bit of [mh]context or with the least significant one.

From the position of the field (mhselect[2] is the 25th bit of textra32 and mhvalue spans bits 26 through 31) it seems like mhselect[2] is compared with the LSB.

Is the interpretation correct? Can this be clarified?

[en-sc]

I've posted a suggestion on how to clarify the spec in #1139
Please, take a look.

[pdonahue-ventana]

The interpretation is correct. It looks like I'm the one who added this syntax in 7aa5978. That expression is valid Verilog syntax and is similar MSB-to-LSB syntax that I've seen in other languages (or in string concatenations in other languages).

We can clarify in a later update to the spec. Because it's ratified, we can't just approve the PR. There's a process to go through and the intention is to wait to batch up a bunch of clarifications before going through that process.