The byte order for each of every 16-byte MSI PTE

[Chen-rui55]

As described in Section 8.5 of the spec:

Every 16-byte MSI PTE is interpreted as two 64-bit doublewords. If an IOMMU also references
standard RISC-V page tables, defined by the RISC-V Privileged Architecture, for regular address
translation, then the byte order for each of the two doublewords in memory, little-endian or big-endian,

The question here is: does this "byte order" refer to the endianness applied to the two doublewords as a whole, or is it applied to each doubleword individually, similar to the IOMMU DC table?

Based on the phrasing in the spec – "byte order for each of the two doublewords in memory" – it seems to indicate that endianness is applied to two doubleword, treating the two doublewords as a single 128-bit unit for byte ordering.