Writes to sourcecfg clearing pending bits

[pkennedyTT]

Section 4.5.2 of the AIA states (emphasis mine):

Any write to a sourcecfg register might (or might not) cause the corresponding interrupt-pending bit to be set to one if the rectified input value is high (= 1) under the new source mode. A write to a sourcecfg register will not by itself cause a pending bit to be cleared except when the source is made inactive. (But see Section 4.7.)

In my mind, the second sentence means that if the pending bit for a given source was set before a write to sourcecfg, then it will remain set after the write to sourcecfg unless that write makes the source inactive, even if the source is level-sensitive and the source's rectified input value is low under the new source mode.

However, section 4.7 says (I've used ellipses because the statement is true both delivery modes):

If the source mode is Level1 or Level0 [...] the pending bit is cleared whenever the rectified input value is low [...]

It further states:

When an interrupt domain is in direct delivery mode, the pending bit for a level-sensitive source is always just a copy of the rectified input value. Even in MSI delivery mode, the pending bit for a level-sensitive source is never set (= 1) when the rectified input value is low.

These statements contradict section 4.5.2 in the scenario where the sourcecfg corresponding to a source with a set pending bit is written to with a source mode such that the rectified input value becomes low (but still active). Section 4.5.2 says that this write will not cause the pending bit to be cleared, but 4.7 requires that it does.

Example scenario:

• Source i has source mode of Edge1
• Source i input value goes from low to high, thus becoming pending
• sourcecfg<i> is written such that source mode changes to Level0, at which point the rectified input value becomes low