Merge pull request rivosinc#1 from rivosinc/dev/joy/add_get_fpr

Added Hammer::get_fpr() and added an a Python API check for Hammer::get_csr()

Author: jerinjoy

hammer.cpp

@@ -84,6 +84,16 @@ void Hammer::set_gpr(uint8_t hart_id, uint8_t gpr_id, reg_t new_gpr_value) {
   hart_state->XPR.write(gpr_id, new_gpr_value);
 }
 
+uint64_t Hammer::get_fpr(uint8_t hart_id, uint8_t fpr_id) {
+  assert(fpr_id < NFPR);
+
+  processor_t *hart = simulator->get_core(hart_id);
+  state_t *hart_state = hart->get_state();
+  freg_t fpr_value = hart_state->FPR[fpr_id];
+
+  return fpr_value.v[0];
+}
+
 reg_t Hammer::get_PC(uint8_t hart_id) {
   processor_t *hart = simulator->get_core(hart_id);
   state_t *hart_state = hart->get_state();
@@ -108,6 +118,11 @@ void Hammer::single_step(uint8_t hart_id) {
   hart->step(1);
 }
 
+uint32_t Hammer::get_flen(uint8_t hart_id) {
+  processor_t *hart = simulator->get_core(hart_id);
+  return hart->get_flen();
+}
+
 reg_t Hammer::get_vlen(uint8_t hart_id) {
   processor_t *hart = simulator->get_core(hart_id);
   return hart->VU.get_vlen();
@@ -119,6 +134,8 @@ reg_t Hammer::get_elen(uint8_t hart_id) {
 }
 
 std::vector<uint64_t> Hammer::get_vector_reg(uint8_t hart_id, uint8_t vector_reg_id) {
+  assert(vector_reg_id < NVPR);
+
   processor_t *hart = simulator->get_core(hart_id);
   uint32_t vlen = hart->VU.get_vlen();
 

hammer.h

@@ -19,13 +19,17 @@ class Hammer {
   reg_t get_gpr(uint8_t hart_id, uint8_t gpr_id);
   void set_gpr(uint8_t hart_id, uint8_t gpr_id, reg_t new_gpr_value);
 
+  uint64_t get_fpr(uint8_t hart_id, uint8_t fpr_id);
+
   reg_t get_PC(uint8_t hart_id);
   void set_PC(uint8_t hart_id, reg_t new_pc_value);
 
   reg_t get_csr(uint8_t hart_id, uint32_t csr_id);
 
   void single_step(uint8_t hart_id);
 
+  uint32_t get_flen(uint8_t hart_id);
+
   reg_t get_vlen(uint8_t hart_id);
   reg_t get_elen(uint8_t hart_id);
 

hammer_pybind.cpp

@@ -21,9 +21,11 @@ PYBIND11_MODULE(hammer, m) {
       .def("hello_world", &Hammer::hello_world)
       .def("get_gpr", &Hammer::get_gpr)
       .def("set_gpr", &Hammer::set_gpr)
+      .def("get_fpr", &Hammer::get_fpr)
       .def("get_PC", &Hammer::get_PC)
       .def("set_PC", &Hammer::set_PC)
       .def("get_csr", &Hammer::get_csr)
+      .def("get_flen", &Hammer::get_flen)
       .def("get_vlen", &Hammer::get_vlen)
       .def("get_elen", &Hammer::get_elen)
       .def("get_vector_reg", &Hammer::get_vector_reg)
@@ -36,4 +38,6 @@ PYBIND11_MODULE(hammer, m) {
   pybind11::enum_<PlatformDefines>(m, "PlatformDefines")
       .value("DramBase", DramBase)
       .export_values();
+
+  pybind11::enum_<CsrDefines>(m, "CsrDefines").value("MSTATUS_CSR", MSTATUS_CSR).export_values();
 }

pytests/meson.build

@@ -16,7 +16,7 @@ riscv_compiler_parameters = [
 ]
 
 hammer_tests = [
-                ['get GPR, CSR and VecReg values', 'pytest000'],
+                ['get GPR, FPR, CSR and VecReg values', 'pytest000'],
                 ['set GPR values', 'pytest001'],
                 ['get/set memory contents', 'pytest002'],
                 ['set PC', 'pytest003']

pytests/pytest000.py

@@ -28,6 +28,10 @@ def main():
     hammer = pyhammer.Hammer("RV64GCV", "MSU", "vlen:512,elen:64", hart_ids, [mem_layout], elf_name,
                              None)
 
+    flen = hammer.get_flen(0)
+    if (flen != 64):
+        sys.exit(f"Unexpected flen: {flen}")
+
     vlen = hammer.get_vlen(0)
     if (vlen != 512):
         sys.exit(f"Unexpected vlen: {vlen}")
@@ -58,10 +62,13 @@ def main():
     if (current_x3 != 3):
         sys.exit(f'Unexpected x3: {current_x3}')
 
-    for _ in range(12):
+    for _ in range(13):
         hammer.single_step(0)
 
-    # TODO: add a read of the mstatus CSR which is set by this point
+    current_mstatus = hammer.get_csr(0, pyhammer.MSTATUS_CSR)
+    if (current_mstatus != 0x8000000a00002600):
+        sys.exit(f"Unexpected mstatus: {current_mstatus:x}")
+
     current_x1 = hammer.get_gpr(0, 1)
     if (current_x1 != 4):
         sys.exit(f'Unexpected x1 after vsetivli {current_x1}')
@@ -87,6 +94,13 @@ def main():
     if (v3[0] != 0x3000 or v3[1] != 0x0 or v3[2] != 0x0 or v3[3] != 0):
         sys.exit(f"Unexpected value in v3: 0x{v3[3]:x}{v3[2]:x}{v3[1]:x}{v3[0]:x}")
 
+    for _ in range(2):
+        hammer.single_step(0)
+
+    current_f1 = hammer.get_fpr(0, 1)
+    if (current_f1 != 0xffffffff3fc00000):
+        sys.exit(f"Unexpected f1: {current_f1:x}")
+
     pass
 
 

tests/meson.build

@@ -21,7 +21,7 @@ else
 endif
 
 hammer_tests = [
-                ['get GPR, CSR and VecReg values', 'test000'],
+                ['get GPR, FPR CSR and VecReg values', 'test000'],
                 ['set GPR values', 'test001'],
                 ['get/set memory contents', 'test002'],
                 ['set PC', 'test003'],

tests/test000.cpp

@@ -18,6 +18,12 @@ int main(int argc, char *argv[]) {
                          target_binary, std::nullopt);
 
   // hammer.hello_world();
+  uint32_t flen = hammer.get_flen(0);
+  if (flen != 64) {
+    printf("Unexpected flen: %d\n", flen);
+    exit(1);
+  }
+
   uint32_t vlen = hammer.get_vlen(0);
   if (vlen != 512) {
     printf("Unexpected vlen: %d\n", vlen);
@@ -59,13 +65,12 @@ int main(int argc, char *argv[]) {
     exit(1);
   }
 
-  for (uint32_t i = 0; i < 12; ++i) {
+  for (uint32_t i = 0; i < 13; ++i) {
     hammer.single_step(0);
   }
 
-  // TODO: add a read of the mstatus CSR which is set by this point
   reg_t current_mstatus = hammer.get_csr(0, MSTATUS_CSR);
-  if (current_mstatus != 0x8000000a00000600) {
+  if (current_mstatus != 0x8000000a00002600) {
     printf("Unexpected mstatus: 0x%" PRIx64 "\n", current_mstatus);
     exit(1);
   }
@@ -111,4 +116,14 @@ int main(int argc, char *argv[]) {
            v3[1], v3[0]);
     exit(1);
   }
+
+  for (uint32_t i = 0; i < 2; ++i) {
+    hammer.single_step(0);
+  }
+
+  uint64_t current_f1 = hammer.get_fpr(0, 1);
+  if (current_f1 != 0xffffffff3fc00000) {
+    printf("Unexpected f1: 0x%" PRIx64 "\n", current_f1);
+    exit(1);
+  }
 }

tests/test000.input.S

@@ -11,7 +11,7 @@ _start:
   li  x2, 2
   add x3, x2, x1; # x3 = x2 + x1
 
-  li  a3, 0x0000000a00000200
+  li  a3, 0xa00002200
   csrw    mstatus, a3
 
   vsetivli x1, 4, e32, m1
@@ -27,6 +27,9 @@ _start:
 
   vadd.vv v3, v2, v1
 
+  li x1, 0x3fc00000
+  fmv.w.x f1, x1
+
   # Magic instruction to terminate the run.
   lui x0, 0xdeadb