From 6c5bdc589a57dbf553887e3af3e8dd13f77241f5 Mon Sep 17 00:00:00 2001
From: root <2022ee19@gmail.com>
Date: Sat, 5 Jul 2025 12:25:50 +0000
Subject: [PATCH 1/2] docs(Q): add quad-precision instruction metadata

Add `long_name`, `description`, and `normative` fields for Q extension instructions
including `fsgnjn.q`, `froundnx.q`, `fmaxm.q`, `fmvp.q.x`, `fmvh.x.q`, and `fnmadd.q`.

Descriptions are taken verbatim from the RISC-V ISA specification where applicable,
and are marked `normative: true` accordingly. Naming and format follow UnifiedDB conventions.
---
 spec/std/isa/inst/Q/fclass.q.yaml   | 32 ++++++++++++++++++++++++++---
 spec/std/isa/inst/Q/fdiv.q.yaml     | 16 ++++++++++++---
 spec/std/isa/inst/Q/feq.q.yaml      | 14 ++++++++++---
 spec/std/isa/inst/Q/fle.q.yaml      | 14 ++++++++++---
 spec/std/isa/inst/Q/fleq.q.yaml     | 14 ++++++++++---
 spec/std/isa/inst/Q/fli.q.yaml      | 12 ++++++++---
 spec/std/isa/inst/Q/flq.yaml        | 14 ++++++++++---
 spec/std/isa/inst/Q/flt.q.yaml      | 14 ++++++++++---
 spec/std/isa/inst/Q/fltq.q.yaml     | 14 ++++++++++---
 spec/std/isa/inst/Q/fmadd.q.yaml    | 13 +++++++++---
 spec/std/isa/inst/Q/fmax.q.yaml     | 13 +++++++++---
 spec/std/isa/inst/Q/fmaxm.q.yaml    | 14 ++++++++++---
 spec/std/isa/inst/Q/fmin.q.yaml     | 13 +++++++++---
 spec/std/isa/inst/Q/fminm.q.yaml    | 14 ++++++++++---
 spec/std/isa/inst/Q/fmsub.q.yaml    | 10 ++++++---
 spec/std/isa/inst/Q/fmul.q.yaml     |  9 +++++---
 spec/std/isa/inst/Q/fmvh.x.q.yaml   | 13 +++++++++---
 spec/std/isa/inst/Q/fmvp.q.x.yaml   | 13 +++++++++---
 spec/std/isa/inst/Q/fnmadd.q.yaml   | 11 +++++++---
 spec/std/isa/inst/Q/fnmsub.q.yaml   | 11 +++++++---
 spec/std/isa/inst/Q/fround.q.yaml   | 14 ++++++++++---
 spec/std/isa/inst/Q/froundnx.q.yaml | 10 ++++++---
 spec/std/isa/inst/Q/fsgnj.q.yaml    | 11 +++++++---
 spec/std/isa/inst/Q/fsgnjn.q.yaml   | 11 +++++++---
 spec/std/isa/inst/Q/fsgnjx.q.yaml   | 11 +++++++---
 spec/std/isa/inst/Q/fsq.yaml        | 14 ++++++++++---
 spec/std/isa/inst/Q/fsqrt.q.yaml    |  9 +++++---
 spec/std/isa/inst/Q/fsub.q.yaml     | 10 ++++++---
 28 files changed, 284 insertions(+), 84 deletions(-)

diff --git a/spec/std/isa/inst/Q/fclass.q.yaml b/spec/std/isa/inst/Q/fclass.q.yaml
index 5834f060b..8f4b01b0b 100644
--- a/spec/std/isa/inst/Q/fclass.q.yaml
+++ b/spec/std/isa/inst/Q/fclass.q.yaml
@@ -6,9 +6,35 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fclass.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Classify
+description:
+  - id: inst-fclass.q-behaviour
+    normative: false
+    text: |
+      The `fclass.q` instruction examines the value in floating-point register `rs1` and writes to integer
+      register `rd` a 10-bit mask that indicates the class of the floating-point number.
+
+      The format of the mask is described in table given below. The corresponding bit in `rd`
+      will be set if the property is true and clear otherwise. All other bits in `rd` are cleared.
+
+      Note that exactly one bit in `rd` will be set. `fclass.q` does not set the floating-point
+      exception flags.
+
+      .Format of result of `fclass` instruction.
+      [%autowidth,float="center",align="center",cols="^,<",options="header",]
+      |===
+      |_xd_ bit |Meaning
+      |0 |_fs1_ is latexmath:[$-\infty$].
+      |1 |_fs1_ is a negative normal number.
+      |2 |_fs1_ is a negative subnormal number.
+      |3 |_fs1_ is latexmath:[$-0$].
+      |4 |_fs1_ is latexmath:[$+0$].
+      |5 |_fs1_ is a positive subnormal number.
+      |6 |_fs1_ is a positive normal number.
+      |7 |_fs1_ is latexmath:[$+\infty$].
+      |8 |_fs1_ is a signaling NaN.
+      |9 |_fs1_ is a quiet NaN.
+      |===
 definedBy: Q
 assembly: xd, fs1
 encoding:
diff --git a/spec/std/isa/inst/Q/fdiv.q.yaml b/spec/std/isa/inst/Q/fdiv.q.yaml
index 0083fd01f..e0c87507d 100644
--- a/spec/std/isa/inst/Q/fdiv.q.yaml
+++ b/spec/std/isa/inst/Q/fdiv.q.yaml
@@ -6,9 +6,19 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fdiv.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Divide
+description:
+  - id: inst-fdiv.q-behaviour
+    normative: false
+    text: |
+      The `fdiv.q` performs the quad-precision floating-point division of `fs1` by `fs2` and writes
+      the result to floating-point register `fd`.`
+      The rounding mode is specified by the value in the floating-point Control and Status register (FCSR)
+      or by the value in the `rm` field of the instruction.
+
+      The operation is performed according to the IEEE 754-2008 standard for quad-precision floating-point arithmetic.
+
+      The instruction sets the floating-point exception flags according to the result of the operation.
 definedBy: Q
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/feq.q.yaml b/spec/std/isa/inst/Q/feq.q.yaml
index 475794eec..24be27a2c 100644
--- a/spec/std/isa/inst/Q/feq.q.yaml
+++ b/spec/std/isa/inst/Q/feq.q.yaml
@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: feq.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Equal
+description:
+  - id: inst-feq.q-behaviour
+    normative: false
+    text: |
+      The `feq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+      and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise.
+
+      `feq.q` performs a quiet comparison:
+      it only sets the invalid operation exception flag if either input is a signaling _NaN_.
+      The result is 0 if either operand is _NaN_.
 definedBy: Q
 assembly: xd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fle.q.yaml b/spec/std/isa/inst/Q/fle.q.yaml
index 13d62c714..7ff033103 100644
--- a/spec/std/isa/inst/Q/fle.q.yaml
+++ b/spec/std/isa/inst/Q/fle.q.yaml
@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fle.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Less Than or Equal
+description:
+  - id: inst-fle.q-behaviour
+    normative: false
+    text: |
+      The `fle.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+      and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+
+      `fle.q` performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is,
+      they set the invalid operation exception flag if either input is _NaN_.
+      The result is 0 if either operand is _NaN_.
 definedBy: Q
 assembly: xd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fleq.q.yaml b/spec/std/isa/inst/Q/fleq.q.yaml
index 54d002d77..4eb0a9318 100644
--- a/spec/std/isa/inst/Q/fleq.q.yaml
+++ b/spec/std/isa/inst/Q/fleq.q.yaml
@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fleq.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Less Than or Equal
+description:
+  - id: inst-fleq.q-behaviour
+    normative: false
+    text: |
+      The `fleq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+      and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+
+      `fleq.q` is defined like `fle.q`, except that quiet _NaN_ inputs do not cause the invalid
+      operation exception flag to be set.
+      This instruction is encoded like its `flt` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: xd, fs1, fs2
diff --git a/spec/std/isa/inst/Q/fli.q.yaml b/spec/std/isa/inst/Q/fli.q.yaml
index c76d9b663..2ad2a7c48 100644
--- a/spec/std/isa/inst/Q/fli.q.yaml
+++ b/spec/std/isa/inst/Q/fli.q.yaml
@@ -6,9 +6,15 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fli.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Load Immediate
+description:
+  - id: inst-fli.q-behaviour
+    normative: false
+    text: |
+      The
+      The `fli.q` instruction loads one of 32 quad-precision floating-point constants, encoded in the `rs1`
+      field, into floating-point register `rd`.
+      `fli.q` is encoded like `fmv.w.x`, but with _fmt_ = Q.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, xs1
diff --git a/spec/std/isa/inst/Q/flq.yaml b/spec/std/isa/inst/Q/flq.yaml
index 35dd839b7..3e7a65e7f 100644
--- a/spec/std/isa/inst/Q/flq.yaml
+++ b/spec/std/isa/inst/Q/flq.yaml
@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: flq
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Load
+description:
+  - id: inst-flq-behaviour
+    normative: false
+    text: |
+      The `flq` is the new variant of LOAD-FP, encoded with a new value for the `funct3`.
+
+      `flq` is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128.
+
+      `flq` does not modify the bits being transferred; in particular, the payloads of non-canonical
+      _NaNs_ are preserved.
 definedBy: Q
 assembly: fd, xs1, imm
 encoding:
diff --git a/spec/std/isa/inst/Q/flt.q.yaml b/spec/std/isa/inst/Q/flt.q.yaml
index 3c55ab6bd..30d26c2ed 100644
--- a/spec/std/isa/inst/Q/flt.q.yaml
+++ b/spec/std/isa/inst/Q/flt.q.yaml
@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: flt.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Less Than
+description:
+  - id: inst-flt.q-behaviour
+    normative: false
+    text: |
+      The `flt.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+      and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise.
+
+      `flt.q` performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is,
+      they set the invalid operation exception flag if either input is _NaN_.
+      The result is 0 if either operand is _NaN_.
 definedBy: Q
 assembly: xd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fltq.q.yaml b/spec/std/isa/inst/Q/fltq.q.yaml
index 5f4822299..c6d428f7b 100644
--- a/spec/std/isa/inst/Q/fltq.q.yaml
+++ b/spec/std/isa/inst/Q/fltq.q.yaml
@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fltq.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Quiet Less Than
+description:
+  - id: inst-fltq.q-behaviour
+    normative: false
+    text: |
+      The `fltq.q` performs the specified comparison between floating-point registers `fs1` and `fs2`,
+      and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+
+      `fltq.q` is defined like `flt.q`, except that quiet _NaN_ inputs do not cause the invalid
+      operation exception flag to be set.
+      This instruction is encoded like its `fle` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, fs2
diff --git a/spec/std/isa/inst/Q/fmadd.q.yaml b/spec/std/isa/inst/Q/fmadd.q.yaml
index bab845d11..e7a00d463 100644
--- a/spec/std/isa/inst/Q/fmadd.q.yaml
+++ b/spec/std/isa/inst/Q/fmadd.q.yaml
@@ -6,9 +6,16 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmadd.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Fused Multiply-Add
+description:
+  - id: inst-fmadd.q-behaviour
+    normative: true
+    text: |
+      The `fmadd.q` instruction performs a floating-point multiply-add operation on the values in registers `fs1`, `fs2`, and `fs3`.
+      It computes the result as `(fs1 * fs2) + fs3` and writes the result to the destination register `fd`.
+
+      The fused multiply-add instructions must set the invalid operation exception flag when the
+      multiplicands are latexmath:[$\infty$] and zero, even when the addend is a quiet _NaN_.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fmax.q.yaml b/spec/std/isa/inst/Q/fmax.q.yaml
index c204f5d28..3f4ea3488 100644
--- a/spec/std/isa/inst/Q/fmax.q.yaml
+++ b/spec/std/isa/inst/Q/fmax.q.yaml
@@ -6,9 +6,16 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmax.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Maximum-Number
+description:
+  - id: inst-fmax.q-behaviour
+    normative: false
+    text: |
+      The `fmax.q` instruction writes the larger/maximum of `fs1` and `fs2` to `fd`.
+      The value `-0.0` is considered to be less than the value `+0.0`.
+      If both inputs are _NaN_s, the result is the canonical _NaN_.
+      If only one operand is a _NaN_, the result is the non-_NaN_ operand.
+      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fmaxm.q.yaml b/spec/std/isa/inst/Q/fmaxm.q.yaml
index 30d7be537..43a216819 100644
--- a/spec/std/isa/inst/Q/fmaxm.q.yaml
+++ b/spec/std/isa/inst/Q/fmaxm.q.yaml
@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmaxm.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Maximum-Number with _NaN_ Handling
+description:
+  - id: inst-fmaxm.q-behaviour
+    normative: false
+    text: |
+      The `fmaxm.q` instruction, defined like `fmax.q`, writes the larger/maximum of `fs1` and `fs2` to `fd`.
+      The value `-0.0` is considered to be less than the value `+0.0`.
+      If both inputs are _NaN_s, the result is the canonical _NaN_.
+      If either input is _NaN_, the result is the canonical _NaN_.
+      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
+      This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, fs2
diff --git a/spec/std/isa/inst/Q/fmin.q.yaml b/spec/std/isa/inst/Q/fmin.q.yaml
index f9ca56105..ae6fa30c9 100644
--- a/spec/std/isa/inst/Q/fmin.q.yaml
+++ b/spec/std/isa/inst/Q/fmin.q.yaml
@@ -6,9 +6,16 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmin.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Minimum-Number
+description:
+  - id: inst-fmin.q-behaviour
+    normative: false
+    text: |
+      The `fmin.q` instruction writes the smaller/minimum of `fs1` and `fs2` to `fd`.
+      The value `-0.0` is considered to be less than the value `+0.0`.
+      If both inputs are _NaN_s, the result is the canonical _NaN_.
+      If only one operand is a _NaN_, the result is the non-_NaN_ operand.
+      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fminm.q.yaml b/spec/std/isa/inst/Q/fminm.q.yaml
index f313ca761..4464a7780 100644
--- a/spec/std/isa/inst/Q/fminm.q.yaml
+++ b/spec/std/isa/inst/Q/fminm.q.yaml
@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fminm.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Minimum-Number with _NaN_ Handling
+description:
+  - id: inst-fminm.q-behaviour
+    normative: false
+    text: |
+      The `fminm.q` instruction, defined like `fmin.q`, writes the smaller/minimum of `fs1` and `fs2` to `fd`.
+      The value `-0.0` is considered to be less than the value `+0.0`.
+      If both inputs are _NaN_s, the result is the canonical _NaN_.
+      If either input is _NaN_, the result is the canonical _NaN_.
+      Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
+      This instruction is encoded like its `fminm.q` counterpart, but with instruction bit 14 set to 1.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, fs2
diff --git a/spec/std/isa/inst/Q/fmsub.q.yaml b/spec/std/isa/inst/Q/fmsub.q.yaml
index 260db0ba1..423f358a1 100644
--- a/spec/std/isa/inst/Q/fmsub.q.yaml
+++ b/spec/std/isa/inst/Q/fmsub.q.yaml
@@ -6,9 +6,13 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmsub.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Fused Multiply-Subtract
+description:
+  - id: inst-fmsub.q-behaviour
+    normative: false
+    text: |
+      The `fmsub.q` instruction performs a floating-point multiply-subtract operation on the values in registers `fs1`, `fs2`, and `fs3`.
+      It computes the result as `(fs1 * fs2) - fs3` and writes the result to the destination register `fd`.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fmul.q.yaml b/spec/std/isa/inst/Q/fmul.q.yaml
index cc3f689ac..4d8e3f98e 100644
--- a/spec/std/isa/inst/Q/fmul.q.yaml
+++ b/spec/std/isa/inst/Q/fmul.q.yaml
@@ -6,9 +6,12 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmul.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Multiply
+description:
+  - id: inst-fmul.q-behaviour
+    normative: false
+    text: |
+      `fmul.q` performs quad-precision floating-point multiplication, between `fs1` and `fs2`.
 definedBy: Q
 assembly: fd, fs1, fs2, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fmvh.x.q.yaml b/spec/std/isa/inst/Q/fmvh.x.q.yaml
index 01a6ab5d0..1e3b10197 100644
--- a/spec/std/isa/inst/Q/fmvh.x.q.yaml
+++ b/spec/std/isa/inst/Q/fmvh.x.q.yaml
@@ -6,9 +6,16 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmvh.x.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Move Upper 64 Bits of Quad-Precision Floating-Point to Integer Register
+description:
+  - id: inst-fmvh.x.q-behaviour
+    normative: false
+    text: |
+      The `fmvh.x.q` instruction moves bits `127:64` of floating-point register `fs1` into integer register `xd`.
+      It is encoded in the OP-FP major opcode with _funct3_=0, _rs2_=1, and _funct7_=1110011.
+
+      `fmvh.x.q` is used in conjunction with the existing `fmv.x.d` instruction to move a quad-precision floating-point
+      number to a pair of x-registers.
 definedBy:
   allOf: [Q, Zfa]
 base: 64
diff --git a/spec/std/isa/inst/Q/fmvp.q.x.yaml b/spec/std/isa/inst/Q/fmvp.q.x.yaml
index 6fbf87619..bb047ea2a 100644
--- a/spec/std/isa/inst/Q/fmvp.q.x.yaml
+++ b/spec/std/isa/inst/Q/fmvp.q.x.yaml
@@ -6,9 +6,16 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fmvp.q.x
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Move Integer Pair to Quad-Precision
+description:
+  - id: inst-fmvp.q.x-behaviour
+    normative: false
+    text: |
+      The `fmvp.q.x` instruction moves a double-precision number from a pair of integer registers into
+      a floating-point register.
+      Integer registers xs1 and xs2 supply bits 63:0 and 127:64, respectively; the result is written to
+      floating-point register `fd`.
+      `fmvp.q.x` is encoded in the OP-FP major opcode with _funct3_=0 and _funct7_=1011011.
 definedBy:
   allOf: [Q, Zfa]
 base: 64
diff --git a/spec/std/isa/inst/Q/fnmadd.q.yaml b/spec/std/isa/inst/Q/fnmadd.q.yaml
index 376220463..39fa97b87 100644
--- a/spec/std/isa/inst/Q/fnmadd.q.yaml
+++ b/spec/std/isa/inst/Q/fnmadd.q.yaml
@@ -6,9 +6,14 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fnmadd.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Fused Negate-Multiply-Add
+description:
+  - id: inst-fnmadd.q-behaviour
+    normative: true
+    text: |
+      The `fnmadd.q` instruction multiplies the values in `fs1` and `fs2`, negates the product, adds the
+      value in `fs3`, and writes the final result to `fd`.
+      `fnmadd.q` computes `-(fs1 * fs2) + fs3`.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fnmsub.q.yaml b/spec/std/isa/inst/Q/fnmsub.q.yaml
index 902532e34..c24d4f624 100644
--- a/spec/std/isa/inst/Q/fnmsub.q.yaml
+++ b/spec/std/isa/inst/Q/fnmsub.q.yaml
@@ -6,9 +6,14 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fnmsub.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Fused Negate-Multiply-Subtract
+description:
+  - id: inst-fnmsub.q-behaviour
+    normative: true
+    text: |
+      The `fnmsub.q` instruction multiplies the values in `fs1` and `fs2`, negates the product, subtracts the
+      value in `fs3`, and writes the final result to `fd`.
+      `fnmsub.q` computes `-(fs1 * fs2) - fs3`.
 definedBy: Q
 assembly: fd, fs1, fs2, fs3, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fround.q.yaml b/spec/std/isa/inst/Q/fround.q.yaml
index d57b8882c..fd51951fd 100644
--- a/spec/std/isa/inst/Q/fround.q.yaml
+++ b/spec/std/isa/inst/Q/fround.q.yaml
@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fround.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Round
+description:
+  - id: inst-fround.q-behaviour
+    normative: false
+    text: |
+      The `fround.q` instruction rounds the quad-precision floating-point number in floating-point register
+      `fs1` to an integer, according to the rounding mode specified in the instruction's `rm` field. It then writes
+      that integer, represented as a quad-precision floating-point number, to floating-point register `fd`. Zero
+      and infinite inputs are copied to `fd` unmodified. Signaling _NaN_ inputs cause the invalid operation
+      exception flag to be set; no other exception flags are set. `fround.q` is encoded like `fcvt.q.s`, but with
+      `rs2`=4.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, rm
diff --git a/spec/std/isa/inst/Q/froundnx.q.yaml b/spec/std/isa/inst/Q/froundnx.q.yaml
index f6586f246..63024b915 100644
--- a/spec/std/isa/inst/Q/froundnx.q.yaml
+++ b/spec/std/isa/inst/Q/froundnx.q.yaml
@@ -6,9 +6,13 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: froundnx.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Round-to-Integral-Exact
+description:
+  - id: inst-froundnx.q-behaviour
+    normative: false
+    text: |
+      The `froundnx.q` instruction is encoded like `fround.q` but with `rs2`=5 and it also sets the
+      inexact exception flag if the input differs from the rounded result and is not _NaN_.
 definedBy:
   allOf: [Q, Zfa]
 assembly: fd, fs1, rm
diff --git a/spec/std/isa/inst/Q/fsgnj.q.yaml b/spec/std/isa/inst/Q/fsgnj.q.yaml
index 8f6057fe5..b9410cb64 100644
--- a/spec/std/isa/inst/Q/fsgnj.q.yaml
+++ b/spec/std/isa/inst/Q/fsgnj.q.yaml
@@ -6,9 +6,14 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fsgnj.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Sign-Injection
+description:
+  - id: inst-fsgnj.q-behaviour
+    normative: false
+    text: |
+      The `fsgnj.q` instruction produces a result that takes all bits except the sign bit from `fs1`.
+      The result's sign bit is taken from `fs2`'s sign bit, and the result is written to the destination register `fd`.
+      `fsgnj.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fsgnjn.q.yaml b/spec/std/isa/inst/Q/fsgnjn.q.yaml
index a456ec710..924ec6686 100644
--- a/spec/std/isa/inst/Q/fsgnjn.q.yaml
+++ b/spec/std/isa/inst/Q/fsgnjn.q.yaml
@@ -6,9 +6,14 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fsgnjn.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Sign Inject Negate
+description:
+  - id: inst-fsgnjn.q-behaviour
+    normative: false
+    text: |
+      The `fsgnjn.q` instruction produces a result that takes all bits except the sign bit from `fs1`.
+      The result's sign bit is opposite of `fs2`'s sign bit, and the result is written to the destination register `fd`.
+      `fsgnjn.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fsgnjx.q.yaml b/spec/std/isa/inst/Q/fsgnjx.q.yaml
index 6d51e6134..123e5369e 100644
--- a/spec/std/isa/inst/Q/fsgnjx.q.yaml
+++ b/spec/std/isa/inst/Q/fsgnjx.q.yaml
@@ -6,9 +6,14 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fsgnjx.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-Point Quad-Precision Sign Inject XOR
+description:
+  - id: inst-fsgnjx.q-behaviour
+    normative: false
+    text: |
+      The `fsgnjx.q` instruction produces a result that takes all bits except the sign bit from `fs1`.
+      The result's sign bit is the XOR of sign bits of `fs1` and `fs2`, and the result is written to the destination register `fd`.
+      `fsgnjx.q` does not set floating-point exception flags, nor do they canonicalize _NaN_s.
 definedBy: Q
 assembly: fd, fs1, fs2
 encoding:
diff --git a/spec/std/isa/inst/Q/fsq.yaml b/spec/std/isa/inst/Q/fsq.yaml
index c5ac626a8..633ac1e55 100644
--- a/spec/std/isa/inst/Q/fsq.yaml
+++ b/spec/std/isa/inst/Q/fsq.yaml
@@ -6,9 +6,17 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fsq
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Store
+description:
+  - id: inst-fsq-behaviour
+    normative: false
+    text: |
+      The `fsq` is the new variant of LOAD-FP, encoded with a new value for the `funct3`.
+
+      `fsq` is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128.
+
+      `fsq` does not modify the bits being transferred; in particular, the payloads of non-canonical
+      _NaNs_ are preserved.
 definedBy: Q
 assembly: fs2, imm(xs1)
 encoding:
diff --git a/spec/std/isa/inst/Q/fsqrt.q.yaml b/spec/std/isa/inst/Q/fsqrt.q.yaml
index 52a2aadce..ef6c562d7 100644
--- a/spec/std/isa/inst/Q/fsqrt.q.yaml
+++ b/spec/std/isa/inst/Q/fsqrt.q.yaml
@@ -6,9 +6,12 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fsqrt.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Square Root
+description:
+  - id: inst-fsqrt.q-behaviour
+    normative: false
+    text: |
+      The `fsqrt.q` instruction computes the square root of the value in `fs1` and writes the result to `fd`.
 definedBy: Q
 assembly: fd, fs1, rm
 encoding:
diff --git a/spec/std/isa/inst/Q/fsub.q.yaml b/spec/std/isa/inst/Q/fsub.q.yaml
index 065dd76f7..d87ae0c75 100644
--- a/spec/std/isa/inst/Q/fsub.q.yaml
+++ b/spec/std/isa/inst/Q/fsub.q.yaml
@@ -6,9 +6,13 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fsub.q
-long_name: No synopsis available
-description: |
-  No description available.
+long_name: Floating-point Quad-Precision Subtract
+description:
+  - id: inst-fsub.q-behaviour
+    normative: false
+    text: |
+      The `fsub.q` instruction performs the quad-precision floating-point subtraction of `fs2` from `fs1`.
+      It computes the result as `fs1 - fs2` and writes the result to the destination register `fd`.
 definedBy: Q
 assembly: fd, fs1, fs2, rm
 encoding:

From c32aa36102dc076d0f4011d37264c4bdc16aca38 Mon Sep 17 00:00:00 2001
From: root <2022ee19@gmail.com>
Date: Sat, 5 Jul 2025 18:45:12 +0000
Subject: [PATCH 2/2] fix: regenerate instruction appendix golden reference

---
 .../all_instructions.golden.adoc              | 230 +++++++++++++-----
 1 file changed, 173 insertions(+), 57 deletions(-)

diff --git a/backends/instructions_appendix/all_instructions.golden.adoc b/backends/instructions_appendix/all_instructions.golden.adoc
index c1e8d2fd9..e71dfe3bf 100644
--- a/backends/instructions_appendix/all_instructions.golden.adoc
+++ b/backends/instructions_appendix/all_instructions.golden.adoc
@@ -1,6 +1,6 @@
 = Instruction Appendix
 :doctype: book
-:wavedrom: /workspace/riscv-unified-db/node_modules/.bin/wavedrom-cli
+:wavedrom: /workspaces/riscv-unified-db/node_modules/.bin/wavedrom-cli
 // Now the document header is complete and the wavedrom attribute is active.
 
 
@@ -7492,7 +7492,7 @@ Included in::
 == fclass.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Classify
 
 Assembly::
 fclass.q xd, fs1
@@ -7504,7 +7504,30 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fclass_q.adoc#udb:doc:inst:fclass_q[fclass.q] instruction examines the value in floating-point register `rs1` and writes to integer
+register `rd` a 10-bit mask that indicates the class of the floating-point number.
+
+The format of the mask is described in table given below. The corresponding bit in `rd`
+will be set if the property is true and clear otherwise. All other bits in `rd` are cleared.
+
+Note that exactly one bit in `rd` will be set. xref:insts:fclass_q.adoc#udb:doc:inst:fclass_q[fclass.q] does not set the floating-point
+exception flags.
+
+.Format of result of `fclass` instruction.
+[%autowidth,float="center",align="center",cols="^,<",options="header",]
+|===
+|_xd_ bit |Meaning
+|0 |_fs1_ is latexmath:[$-\infty$].
+|1 |_fs1_ is a negative normal number.
+|2 |_fs1_ is a negative subnormal number.
+|3 |_fs1_ is latexmath:[$-0$].
+|4 |_fs1_ is latexmath:[$+0$].
+|5 |_fs1_ is a positive subnormal number.
+|6 |_fs1_ is a positive normal number.
+|7 |_fs1_ is latexmath:[$+\infty$].
+|8 |_fs1_ is a signaling NaN.
+|9 |_fs1_ is a quiet NaN.
+|===
 
 
 Decode Variables::
@@ -9577,7 +9600,7 @@ Included in::
 == fdiv.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Divide
 
 Assembly::
 fdiv.q fd, fs1, fs2, rm
@@ -9589,7 +9612,14 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fdiv_q.adoc#udb:doc:inst:fdiv_q[fdiv.q] performs the quad-precision floating-point division of `fs1` by `fs2` and writes
+the result to floating-point register `fd`.`
+The rounding mode is specified by the value in the floating-point Control and Status register (FCSR)
+or by the value in the `rm` field of the instruction.
+
+The operation is performed according to the IEEE 754-2008 standard for quad-precision floating-point arithmetic.
+
+The instruction sets the floating-point exception flags according to the result of the operation.
 
 
 Decode Variables::
@@ -9989,7 +10019,7 @@ Included in::
 == feq.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Equal
 
 Assembly::
 feq.q xd, fs1, fs2
@@ -10001,7 +10031,12 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:feq_q.adoc#udb:doc:inst:feq_q[feq.q] performs the specified comparison between floating-point registers `fs1` and `fs2`,
+and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise.
+
+xref:insts:feq_q.adoc#udb:doc:inst:feq_q[feq.q] performs a quiet comparison:
+it only sets the invalid operation exception flag if either input is a signaling _NaN_.
+The result is 0 if either operand is _NaN_.
 
 
 Decode Variables::
@@ -10183,7 +10218,7 @@ Included in::
 == fle.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Less Than or Equal
 
 Assembly::
 fle.q xd, fs1, fs2
@@ -10195,7 +10230,12 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fle_q.adoc#udb:doc:inst:fle_q[fle.q] performs the specified comparison between floating-point registers `fs1` and `fs2`,
+and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+
+xref:insts:fle_q.adoc#udb:doc:inst:fle_q[fle.q] performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is,
+they set the invalid operation exception flag if either input is _NaN_.
+The result is 0 if either operand is _NaN_.
 
 
 Decode Variables::
@@ -10344,7 +10384,7 @@ Included in::
 == fleq.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Less Than or Equal
 
 Assembly::
 fleq.q xd, fs1, fs2
@@ -10356,7 +10396,12 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fleq_q.adoc#udb:doc:inst:fleq_q[fleq.q] performs the specified comparison between floating-point registers `fs1` and `fs2`,
+and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+
+xref:insts:fleq_q.adoc#udb:doc:inst:fleq_q[fleq.q] is defined like xref:insts:fle_q.adoc#udb:doc:inst:fle_q[fle.q], except that quiet _NaN_ inputs do not cause the invalid
+operation exception flag to be set.
+This instruction is encoded like its `flt` counterpart, but with instruction bit 14 set to 1.
 
 
 Decode Variables::
@@ -10546,7 +10591,7 @@ Included in::
 == fli.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Load Immediate
 
 Assembly::
 fli.q fd, xs1
@@ -10558,7 +10603,10 @@ Encoding::
 ....
 
 Description::
-No description available.
+The
+The xref:insts:fli_q.adoc#udb:doc:inst:fli_q[fli.q] instruction loads one of 32 quad-precision floating-point constants, encoded in the `rs1`
+field, into floating-point register `rd`.
+xref:insts:fli_q.adoc#udb:doc:inst:fli_q[fli.q] is encoded like xref:insts:fmv_w_x.adoc#udb:doc:inst:fmv_w_x[fmv.w.x], but with _fmt_ = Q.
 
 
 Decode Variables::
@@ -10622,7 +10670,7 @@ Included in::
 == flq
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Load
 
 Assembly::
 flq fd, xs1, imm
@@ -10634,7 +10682,12 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:flq.adoc#udb:doc:inst:flq[flq] is the new variant of LOAD-FP, encoded with a new value for the `funct3`.
+
+xref:insts:flq.adoc#udb:doc:inst:flq[flq] is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128.
+
+xref:insts:flq.adoc#udb:doc:inst:flq[flq] does not modify the bits being transferred; in particular, the payloads of non-canonical
+_NaNs_ are preserved.
 
 
 Decode Variables::
@@ -10736,7 +10789,7 @@ Included in::
 == flt.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Less Than
 
 Assembly::
 flt.q xd, fs1, fs2
@@ -10748,7 +10801,12 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:flt_q.adoc#udb:doc:inst:flt_q[flt.q] performs the specified comparison between floating-point registers `fs1` and `fs2`,
+and writes 1 to integer register `xd` if the conditon hold, and 0 otherwise.
+
+xref:insts:flt_q.adoc#udb:doc:inst:flt_q[flt.q] performs what the IEEE 754-2008 standard refers to as signaling comparisons: that is,
+they set the invalid operation exception flag if either input is _NaN_.
+The result is 0 if either operand is _NaN_.
 
 
 Decode Variables::
@@ -10895,7 +10953,7 @@ Included in::
 == fltq.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Quiet Less Than
 
 Assembly::
 fltq.q fd, fs1, fs2
@@ -10907,7 +10965,12 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fltq_q.adoc#udb:doc:inst:fltq_q[fltq.q] performs the specified comparison between floating-point registers `fs1` and `fs2`,
+and writes 1 to integer register `xd` if the condition holds, and 0 otherwise.
+
+xref:insts:fltq_q.adoc#udb:doc:inst:fltq_q[fltq.q] is defined like xref:insts:flt_q.adoc#udb:doc:inst:flt_q[flt.q], except that quiet _NaN_ inputs do not cause the invalid
+operation exception flag to be set.
+This instruction is encoded like its `fle` counterpart, but with instruction bit 14 set to 1.
 
 
 Decode Variables::
@@ -11093,7 +11156,7 @@ Included in::
 == fmadd.q
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Fused Multiply-Add
 
 Assembly::
 fmadd.q fd, fs1, fs2, fs3, rm
@@ -11105,7 +11168,11 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fmadd_q.adoc#udb:doc:inst:fmadd_q[fmadd.q] instruction performs a floating-point multiply-add operation on the values in registers `fs1`, `fs2`, and `fs3`.
+It computes the result as `(fs1 * fs2) + fs3` and writes the result to the destination register `fd`.
+
+The fused multiply-add instructions must set the invalid operation exception flag when the
+multiplicands are latexmath:[$\infty$] and zero, even when the addend is a quiet _NaN_.
 
 
 Decode Variables::
@@ -11249,7 +11316,7 @@ Included in::
 == fmax.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Maximum-Number
 
 Assembly::
 fmax.q fd, fs1, fs2
@@ -11261,7 +11328,11 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fmax_q.adoc#udb:doc:inst:fmax_q[fmax.q] instruction writes the larger/maximum of `fs1` and `fs2` to `fd`.
+The value `-0.0` is considered to be less than the value `+0.0`.
+If both inputs are _NaN_s, the result is the canonical _NaN_.
+If only one operand is a _NaN_, the result is the non-_NaN_ operand.
+Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
 
 
 Decode Variables::
@@ -11405,7 +11476,7 @@ Included in::
 == fmaxm.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Maximum-Number with _NaN_ Handling
 
 Assembly::
 fmaxm.q fd, fs1, fs2
@@ -11417,7 +11488,12 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fmaxm_q.adoc#udb:doc:inst:fmaxm_q[fmaxm.q] instruction, defined like xref:insts:fmax_q.adoc#udb:doc:inst:fmax_q[fmax.q], writes the larger/maximum of `fs1` and `fs2` to `fd`.
+The value `-0.0` is considered to be less than the value `+0.0`.
+If both inputs are _NaN_s, the result is the canonical _NaN_.
+If either input is _NaN_, the result is the canonical _NaN_.
+Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
+This instruction is encoded like its xref:insts:fminm_q.adoc#udb:doc:inst:fminm_q[fminm.q] counterpart, but with instruction bit 14 set to 1.
 
 
 Decode Variables::
@@ -11559,7 +11635,7 @@ Included in::
 == fmin.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Minimum-Number
 
 Assembly::
 fmin.q fd, fs1, fs2
@@ -11571,7 +11647,11 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fmin_q.adoc#udb:doc:inst:fmin_q[fmin.q] instruction writes the smaller/minimum of `fs1` and `fs2` to `fd`.
+The value `-0.0` is considered to be less than the value `+0.0`.
+If both inputs are _NaN_s, the result is the canonical _NaN_.
+If only one operand is a _NaN_, the result is the non-_NaN_ operand.
+Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
 
 
 Decode Variables::
@@ -11715,7 +11795,7 @@ Included in::
 == fminm.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Minimum-Number with _NaN_ Handling
 
 Assembly::
 fminm.q fd, fs1, fs2
@@ -11727,7 +11807,12 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fminm_q.adoc#udb:doc:inst:fminm_q[fminm.q] instruction, defined like xref:insts:fmin_q.adoc#udb:doc:inst:fmin_q[fmin.q], writes the smaller/minimum of `fs1` and `fs2` to `fd`.
+The value `-0.0` is considered to be less than the value `+0.0`.
+If both inputs are _NaN_s, the result is the canonical _NaN_.
+If either input is _NaN_, the result is the canonical _NaN_.
+Signaling _NaN_ inputs set the invalid operation exception flag, even when the result is not _NaN_.
+This instruction is encoded like its xref:insts:fminm_q.adoc#udb:doc:inst:fminm_q[fminm.q] counterpart, but with instruction bit 14 set to 1.
 
 
 Decode Variables::
@@ -11873,7 +11958,7 @@ Included in::
 == fmsub.q
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Fused Multiply-Subtract
 
 Assembly::
 fmsub.q fd, fs1, fs2, fs3, rm
@@ -11885,7 +11970,8 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fmsub_q.adoc#udb:doc:inst:fmsub_q[fmsub.q] instruction performs a floating-point multiply-subtract operation on the values in registers `fs1`, `fs2`, and `fs3`.
+It computes the result as `(fs1 * fs2) - fs3` and writes the result to the destination register `fd`.
 
 
 Decode Variables::
@@ -12031,7 +12117,7 @@ Included in::
 == fmul.q
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Multiply
 
 Assembly::
 fmul.q fd, fs1, fs2, rm
@@ -12043,7 +12129,7 @@ Encoding::
 ....
 
 Description::
-No description available.
+xref:insts:fmul_q.adoc#udb:doc:inst:fmul_q[fmul.q] performs quad-precision floating-point multiplication, between `fs1` and `fs2`.
 
 
 Decode Variables::
@@ -12392,7 +12478,7 @@ Included in::
 == fmvh.x.q
 
 Synopsis::
-No synopsis available
+Move Upper 64 Bits of Quad-Precision Floating-Point to Integer Register
 
 Assembly::
 fmvh.x.q xd, fs1
@@ -12404,7 +12490,11 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fmvh_x_q.adoc#udb:doc:inst:fmvh_x_q[fmvh.x.q] instruction moves bits `127:64` of floating-point register `fs1` into integer register `xd`.
+It is encoded in the OP-FP major opcode with _funct3_=0, _rs2_=1, and _funct7_=1110011.
+
+xref:insts:fmvh_x_q.adoc#udb:doc:inst:fmvh_x_q[fmvh.x.q] is used in conjunction with the existing xref:insts:fmv_x_d.adoc#udb:doc:inst:fmv_x_d[fmv.x.d] instruction to move a quad-precision floating-point
+number to a pair of x-registers.
 
 
 Decode Variables::
@@ -12471,7 +12561,7 @@ Included in::
 == fmvp.q.x
 
 Synopsis::
-No synopsis available
+Floating-point Move Integer Pair to Quad-Precision
 
 Assembly::
 fmvp.q.x fd, xs1, xs2
@@ -12483,7 +12573,11 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fmvp_q_x.adoc#udb:doc:inst:fmvp_q_x[fmvp.q.x] instruction moves a double-precision number from a pair of integer registers into
+a floating-point register.
+Integer registers xs1 and xs2 supply bits 63:0 and 127:64, respectively; the result is written to
+floating-point register `fd`.
+xref:insts:fmvp_q_x.adoc#udb:doc:inst:fmvp_q_x[fmvp.q.x] is encoded in the OP-FP major opcode with _funct3_=0 and _funct7_=1011011.
 
 
 Decode Variables::
@@ -12591,7 +12685,7 @@ Included in::
 == fnmadd.q
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Fused Negate-Multiply-Add
 
 Assembly::
 fnmadd.q fd, fs1, fs2, fs3, rm
@@ -12603,7 +12697,9 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fnmadd_q.adoc#udb:doc:inst:fnmadd_q[fnmadd.q] instruction multiplies the values in `fs1` and `fs2`, negates the product, adds the
+value in `fs3`, and writes the final result to `fd`.
+xref:insts:fnmadd_q.adoc#udb:doc:inst:fnmadd_q[fnmadd.q] computes `-(fs1 * fs2) + fs3`.
 
 
 Decode Variables::
@@ -12751,7 +12847,7 @@ Included in::
 == fnmsub.q
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Fused Negate-Multiply-Subtract
 
 Assembly::
 fnmsub.q fd, fs1, fs2, fs3, rm
@@ -12763,7 +12859,9 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fnmsub_q.adoc#udb:doc:inst:fnmsub_q[fnmsub.q] instruction multiplies the values in `fs1` and `fs2`, negates the product, subtracts the
+value in `fs3`, and writes the final result to `fd`.
+xref:insts:fnmsub_q.adoc#udb:doc:inst:fnmsub_q[fnmsub.q] computes `-(fs1 * fs2) - fs3`.
 
 
 Decode Variables::
@@ -12911,7 +13009,7 @@ Included in::
 == fround.q
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Round
 
 Assembly::
 fround.q fd, fs1, rm
@@ -12923,7 +13021,12 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fround_q.adoc#udb:doc:inst:fround_q[fround.q] instruction rounds the quad-precision floating-point number in floating-point register
+`fs1` to an integer, according to the rounding mode specified in the instruction's `rm` field. It then writes
+that integer, represented as a quad-precision floating-point number, to floating-point register `fd`. Zero
+and infinite inputs are copied to `fd` unmodified. Signaling _NaN_ inputs cause the invalid operation
+exception flag to be set; no other exception flags are set. xref:insts:fround_q.adoc#udb:doc:inst:fround_q[fround.q] is encoded like xref:insts:fcvt_q_s.adoc#udb:doc:inst:fcvt_q_s[fcvt.q.s], but with
+`rs2`=4.
 
 
 Decode Variables::
@@ -13069,7 +13172,7 @@ Included in::
 == froundnx.q
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Round-to-Integral-Exact
 
 Assembly::
 froundnx.q fd, fs1, rm
@@ -13081,7 +13184,8 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:froundnx_q.adoc#udb:doc:inst:froundnx_q[froundnx.q] instruction is encoded like xref:insts:fround_q.adoc#udb:doc:inst:fround_q[fround.q] but with `rs2`=5 and it also sets the
+inexact exception flag if the input differs from the rounded result and is not _NaN_.
 
 
 Decode Variables::
@@ -13261,7 +13365,7 @@ Included in::
 == fsgnj.q
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Sign-Injection
 
 Assembly::
 fsgnj.q fd, fs1, fs2
@@ -13273,7 +13377,9 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fsgnj_q.adoc#udb:doc:inst:fsgnj_q[fsgnj.q] instruction produces a result that takes all bits except the sign bit from `fs1`.
+The result's sign bit is taken from `fs2`'s sign bit, and the result is written to the destination register `fd`.
+xref:insts:fsgnj_q.adoc#udb:doc:inst:fsgnj_q[fsgnj.q] does not set floating-point exception flags, nor do they canonicalize _NaN_s.
 
 
 Decode Variables::
@@ -13415,7 +13521,7 @@ Included in::
 == fsgnjn.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Sign Inject Negate
 
 Assembly::
 fsgnjn.q fd, fs1, fs2
@@ -13427,7 +13533,9 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fsgnjn_q.adoc#udb:doc:inst:fsgnjn_q[fsgnjn.q] instruction produces a result that takes all bits except the sign bit from `fs1`.
+The result's sign bit is opposite of `fs2`'s sign bit, and the result is written to the destination register `fd`.
+xref:insts:fsgnjn_q.adoc#udb:doc:inst:fsgnjn_q[fsgnjn.q] does not set floating-point exception flags, nor do they canonicalize _NaN_s.
 
 
 Decode Variables::
@@ -13569,7 +13677,7 @@ Included in::
 == fsgnjx.q
 
 Synopsis::
-No synopsis available
+Floating-Point Quad-Precision Sign Inject XOR
 
 Assembly::
 fsgnjx.q fd, fs1, fs2
@@ -13581,7 +13689,9 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fsgnjx_q.adoc#udb:doc:inst:fsgnjx_q[fsgnjx.q] instruction produces a result that takes all bits except the sign bit from `fs1`.
+The result's sign bit is the XOR of sign bits of `fs1` and `fs2`, and the result is written to the destination register `fd`.
+xref:insts:fsgnjx_q.adoc#udb:doc:inst:fsgnjx_q[fsgnjx.q] does not set floating-point exception flags, nor do they canonicalize _NaN_s.
 
 
 Decode Variables::
@@ -13696,7 +13806,7 @@ Included in::
 == fsq
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Store
 
 Assembly::
 fsq fs2, imm(xs1)
@@ -13708,7 +13818,12 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fsq.adoc#udb:doc:inst:fsq[fsq] is the new variant of LOAD-FP, encoded with a new value for the `funct3`.
+
+xref:insts:fsq.adoc#udb:doc:inst:fsq[fsq] is only guaranteed to execute atomically if the effective address is naturally aligned XLEN=128.
+
+xref:insts:fsq.adoc#udb:doc:inst:fsq[fsq] does not modify the bits being transferred; in particular, the payloads of non-canonical
+_NaNs_ are preserved.
 
 
 Decode Variables::
@@ -13810,7 +13925,7 @@ Included in::
 == fsqrt.q
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Square Root
 
 Assembly::
 fsqrt.q fd, fs1, rm
@@ -13822,7 +13937,7 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fsqrt_q.adoc#udb:doc:inst:fsqrt_q[fsqrt.q] instruction computes the square root of the value in `fs1` and writes the result to `fd`.
 
 
 Decode Variables::
@@ -13964,7 +14079,7 @@ Included in::
 == fsub.q
 
 Synopsis::
-No synopsis available
+Floating-point Quad-Precision Subtract
 
 Assembly::
 fsub.q fd, fs1, fs2, rm
@@ -13976,7 +14091,8 @@ Encoding::
 ....
 
 Description::
-No description available.
+The xref:insts:fsub_q.adoc#udb:doc:inst:fsub_q[fsub.q] instruction performs the quad-precision floating-point subtraction of `fs2` from `fs1`.
+It computes the result as `fs1 - fs2` and writes the result to the destination register `fd`.
 
 
 Decode Variables::