From 1ee91924627d54d41b11664b01efa5d58594b9c5 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Wed, 23 Apr 2025 23:07:36 +0000 Subject: [PATCH 1/7] add fflags and frm csrs --- arch/csr/F/fflags.yaml | 88 ++++++++++++++++++++++++++++++++++++++++++ arch/csr/F/frm.yaml | 46 ++++++++++++++++++++++ 2 files changed, 134 insertions(+) create mode 100644 arch/csr/F/fflags.yaml create mode 100644 arch/csr/F/frm.yaml diff --git a/arch/csr/F/fflags.yaml b/arch/csr/F/fflags.yaml new file mode 100644 index 000000000..7ebe2ea1b --- /dev/null +++ b/arch/csr/F/fflags.yaml @@ -0,0 +1,88 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: fflags +long_name: Floating-Point Accrued Exceptions +address: 0x001 +description: | + The accrued exception flags indicate the exception conditions that have arisen on any floating-point + arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not + support generating a trap on the setting of a floating-point exception flag. + + [[rm]] + .Accrued Exception Flag Encoding. + [%autowidth,float="center",align="center",cols="^,^,<",options="header"] + !=== + !Flag Mnemonic |Flag Meaning + !NV !Invalid Operation + !DZ !Divide by Zero + !OF !Overflow + !UF !Underflow + !NX !Inexact + !=== + + As allowed by the standard, we do not support traps on floating-point exceptions in the F + extension, but instead require explicit checks of the flags in software. We considered + adding branches controlled directly by the contents of the floating-point accrued exception + flags, but ultimately chose to omit these instructions to keep the ISA simple. + +priv_mode: U +length: 32 +definedBy: F +fields: + NV: + location: 4 + description: | + *Invalid Operation* + + Cumulative error flag for floating point operations. + + Set by hardware when a floating point operation is invalid and stays set until explicitly + cleared by software. + type: RW-H + reset_value: UNDEFINED_LEGAL + DZ: + location: 3 + description: | + *Divide by zero* + + Cumulative error flag for floating point operations. + + Set by hardware when a floating point divide attempts to divide by zero and stays set until explicitly + cleared by software. + type: RW-H + reset_value: UNDEFINED_LEGAL + OF: + location: 2 + description: | + *Overflow* + + Cumulative error flag for floating point operations. + + Set by hardware when a floating point operation overflows and stays set until explicitly + cleared by software. + type: RW-H + reset_value: UNDEFINED_LEGAL + UF: + location: 1 + description: | + *Underflow* + + Cumulative error flag for floating point operations. + + Set by hardware when a floating point operation underflows and stays set until explicitly + cleared by software. + type: RW-H + reset_value: UNDEFINED_LEGAL + NX: + location: 0 + description: | + *Inexact* + + Cumulative error flag for floating point operations. + + Set by hardware when a floating point operation is inexact and stays set until explicitly + cleared by software. + type: RW-H + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/F/frm.yaml b/arch/csr/F/frm.yaml new file mode 100644 index 000000000..34748f277 --- /dev/null +++ b/arch/csr/F/frm.yaml @@ -0,0 +1,46 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: frm +long_name: Floating-Point Dynamic Rounding Mode +address: 0x002 +description: | + Rounding modes are encoded as follows: + + [[rm]] + .Rounding mode encoding. + [%autowidth,float="center",align="center",cols="^,^,<",options="header"] + !=== + !Rounding Mode |Mnemonic |Meaning + !000 !RNE !Round to Nearest, ties to Even + !001 !RTZ !Round towards Zero + !010 !RDN !Round Down (towards latexmath:[$-\infty$]) + !011 !RUP !Round Up (towards latexmath:[$+\infty$]) + !100 !RMM !Round to Nearest, ties to Max Magnitude + !101 ! !_Reserved for future use._ + !110 ! !_Reserved for future use._ + !111 !DYN !In instruction's _rm_ field, selects dynamic rounding mode; In Rounding Mode register, _reserved_. + !=== + + A value of 111 in the + instruction's _rm_ field selects the dynamic rounding mode held in + `frm`. The behavior of floating-point instructions that depend on + rounding mode when executed with a reserved rounding mode is _reserved_, + including both static reserved rounding modes (101-110) and dynamic reserved + rounding modes (101-111). Some instructions, including widening conversions, + have the _rm_ field but are nevertheless mathematically unaffected by the + rounding mode; software should set their _rm_ field to + RNE (000) but implementations must treat the _rm_ field as usual (in + particular, with regard to decoding legal vs. reserved encodings). + +priv_mode: U +length: 32 +definedBy: F +fields: + ROUNDINGMODE: + location: 2-0 + description: | + Rounding mode data. + type: RW-H + reset_value: UNDEFINED_LEGAL From da61f15c465117fd6ce6925cd1da70c3cfddcaa8 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 24 Apr 2025 14:24:07 +0000 Subject: [PATCH 2/7] tag & identifier changes --- arch/csr/F/fflags.yaml | 23 +++++++++++++---------- 1 file changed, 13 insertions(+), 10 deletions(-) diff --git a/arch/csr/F/fflags.yaml b/arch/csr/F/fflags.yaml index 7ebe2ea1b..572373b01 100644 --- a/arch/csr/F/fflags.yaml +++ b/arch/csr/F/fflags.yaml @@ -10,22 +10,25 @@ description: | arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag. - [[rm]] + [[bitdef]] .Accrued Exception Flag Encoding. - [%autowidth,float="center",align="center",cols="^,^,<",options="header"] - !=== - !Flag Mnemonic |Flag Meaning - !NV !Invalid Operation - !DZ !Divide by Zero - !OF !Overflow - !UF !Underflow - !NX !Inexact - !=== + [%autowidth,float="center",align="center",cols="^,<",options="header",] + |=== + |Flag Mnemonic |Flag Meaning + |NV |Invalid Operation + |DZ |Divide by Zero + |OF |Overflow + |UF |Underflow + |NX |Inexact + |=== + [NOTE] + ==== As allowed by the standard, we do not support traps on floating-point exceptions in the F extension, but instead require explicit checks of the flags in software. We considered adding branches controlled directly by the contents of the floating-point accrued exception flags, but ultimately chose to omit these instructions to keep the ISA simple. + ==== priv_mode: U length: 32 From f2b85a3fd5077e2d1d2c9e99300cdb6c5d7cbef6 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Mon, 28 Apr 2025 21:19:34 +0000 Subject: [PATCH 3/7] fixed alias and removed some lines --- arch/csr/F/fflags.yaml | 27 +++++---------------------- arch/csr/F/frm.yaml | 1 + 2 files changed, 6 insertions(+), 22 deletions(-) diff --git a/arch/csr/F/fflags.yaml b/arch/csr/F/fflags.yaml index 572373b01..5c83a3403 100644 --- a/arch/csr/F/fflags.yaml +++ b/arch/csr/F/fflags.yaml @@ -10,18 +10,6 @@ description: | arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag. - [[bitdef]] - .Accrued Exception Flag Encoding. - [%autowidth,float="center",align="center",cols="^,<",options="header",] - |=== - |Flag Mnemonic |Flag Meaning - |NV |Invalid Operation - |DZ |Divide by Zero - |OF |Overflow - |UF |Underflow - |NX |Inexact - |=== - [NOTE] ==== As allowed by the standard, we do not support traps on floating-point exceptions in the F @@ -35,56 +23,51 @@ length: 32 definedBy: F fields: NV: + alias: fcsr.NV location: 4 description: | *Invalid Operation* - Cumulative error flag for floating point operations. - Set by hardware when a floating point operation is invalid and stays set until explicitly cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL DZ: + alias: fcsr.DZ location: 3 description: | *Divide by zero* - Cumulative error flag for floating point operations. - Set by hardware when a floating point divide attempts to divide by zero and stays set until explicitly cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL OF: + alias: fcsr.OF location: 2 description: | *Overflow* - Cumulative error flag for floating point operations. - Set by hardware when a floating point operation overflows and stays set until explicitly cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL UF: + alias: fcsr.UF location: 1 description: | *Underflow* - Cumulative error flag for floating point operations. - Set by hardware when a floating point operation underflows and stays set until explicitly cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL NX: + alias: fcsr.NX location: 0 description: | *Inexact* - Cumulative error flag for floating point operations. - Set by hardware when a floating point operation is inexact and stays set until explicitly cleared by software. type: RW-H diff --git a/arch/csr/F/frm.yaml b/arch/csr/F/frm.yaml index 34748f277..0f29b0381 100644 --- a/arch/csr/F/frm.yaml +++ b/arch/csr/F/frm.yaml @@ -39,6 +39,7 @@ length: 32 definedBy: F fields: ROUNDINGMODE: + alias: fcsr.FRM location: 2-0 description: | Rounding mode data. From 52abb834912201b5519077ccd87abeeb93397de2 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Mon, 28 Apr 2025 22:37:45 +0000 Subject: [PATCH 4/7] added long names to fields --- arch/csr/F/fflags.yaml | 15 +++++---------- 1 file changed, 5 insertions(+), 10 deletions(-) diff --git a/arch/csr/F/fflags.yaml b/arch/csr/F/fflags.yaml index 5c83a3403..bfd424de9 100644 --- a/arch/csr/F/fflags.yaml +++ b/arch/csr/F/fflags.yaml @@ -24,50 +24,45 @@ definedBy: F fields: NV: alias: fcsr.NV + long_name: Invalid Operation location: 4 description: | - *Invalid Operation* - Set by hardware when a floating point operation is invalid and stays set until explicitly cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL DZ: alias: fcsr.DZ + long_name: Divide by Zero location: 3 description: | - *Divide by zero* - Set by hardware when a floating point divide attempts to divide by zero and stays set until explicitly cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL OF: alias: fcsr.OF + long_name: Overflow location: 2 description: | - *Overflow* - Set by hardware when a floating point operation overflows and stays set until explicitly cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL UF: alias: fcsr.UF + long_name: Underflow location: 1 description: | - *Underflow* - Set by hardware when a floating point operation underflows and stays set until explicitly cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL NX: alias: fcsr.NX + long_name: Inexact location: 0 description: | - *Inexact* - Set by hardware when a floating point operation is inexact and stays set until explicitly cleared by software. type: RW-H From b19c0a149f4d1bcbedbd9d0ebd0ea3a63f3c1807 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Wed, 30 Apr 2025 19:02:01 +0000 Subject: [PATCH 5/7] add sw_read --- arch/csr/F/fflags.yaml | 7 +++++++ arch/csr/F/frm.yaml | 3 +++ 2 files changed, 10 insertions(+) diff --git a/arch/csr/F/fflags.yaml b/arch/csr/F/fflags.yaml index bfd424de9..e7b2a79d1 100644 --- a/arch/csr/F/fflags.yaml +++ b/arch/csr/F/fflags.yaml @@ -67,3 +67,10 @@ fields: cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL +sw_read(): | + return + (CSR[fcsr].NV `<< 4) | + (CSR[fcsr].DZ `<< 3) | + (CSR[fcsr].OF `<< 2) | + (CSR[fcsr].UF `<< 1) | + CSR[fcsr].NX; diff --git a/arch/csr/F/frm.yaml b/arch/csr/F/frm.yaml index 0f29b0381..b3ec15b27 100644 --- a/arch/csr/F/frm.yaml +++ b/arch/csr/F/frm.yaml @@ -45,3 +45,6 @@ fields: Rounding mode data. type: RW-H reset_value: UNDEFINED_LEGAL +sw_read(): | + return + CSR[fcsr].FRM; From 8419274a5d9613df59267adfd8453afe2525b189 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 1 May 2025 21:34:07 +0000 Subject: [PATCH 6/7] change description to structured format --- arch/csr/F/fflags.yaml | 28 +++++++++++--------- arch/csr/F/frm.yaml | 59 +++++++++++++++++++++++------------------- 2 files changed, 48 insertions(+), 39 deletions(-) diff --git a/arch/csr/F/fflags.yaml b/arch/csr/F/fflags.yaml index e7b2a79d1..c310f23db 100644 --- a/arch/csr/F/fflags.yaml +++ b/arch/csr/F/fflags.yaml @@ -5,18 +5,22 @@ kind: csr name: fflags long_name: Floating-Point Accrued Exceptions address: 0x001 -description: | - The accrued exception flags indicate the exception conditions that have arisen on any floating-point - arithmetic instruction since the field was last reset by software. The base RISC-V ISA does not - support generating a trap on the setting of a floating-point exception flag. - - [NOTE] - ==== - As allowed by the standard, we do not support traps on floating-point exceptions in the F - extension, but instead require explicit checks of the flags in software. We considered - adding branches controlled directly by the contents of the floating-point accrued exception - flags, but ultimately chose to omit these instructions to keep the ISA simple. - ==== +description: + - id: csr-fflags-purpose + normative: true + text: | + The accrued exception flags indicate the exception conditions that have arisen on any floating-point arithmetic + instruction since the field was last reset by software. + - id: csr-fflags-fptrap + normative: false + text: The base RISC-V ISA does not support generating a trap on the setting of a floating-point exception flag. + - id: csr-fflags-reasoning + normative: false + text: | + As allowed by the standard, we do not support traps on floating-point exceptions in the F + extension, but instead require explicit checks of the flags in software. We considered + adding branches controlled directly by the contents of the floating-point accrued + exception flags, but ultimately chose to omit these instructions to keep the ISA simple. priv_mode: U length: 32 diff --git a/arch/csr/F/frm.yaml b/arch/csr/F/frm.yaml index b3ec15b27..767996536 100644 --- a/arch/csr/F/frm.yaml +++ b/arch/csr/F/frm.yaml @@ -5,34 +5,39 @@ kind: csr name: frm long_name: Floating-Point Dynamic Rounding Mode address: 0x002 -description: | - Rounding modes are encoded as follows: +description: + - id: csr-frm-encodings + normative: false + text: | + Rounding modes are encoded as follows: - [[rm]] - .Rounding mode encoding. - [%autowidth,float="center",align="center",cols="^,^,<",options="header"] - !=== - !Rounding Mode |Mnemonic |Meaning - !000 !RNE !Round to Nearest, ties to Even - !001 !RTZ !Round towards Zero - !010 !RDN !Round Down (towards latexmath:[$-\infty$]) - !011 !RUP !Round Up (towards latexmath:[$+\infty$]) - !100 !RMM !Round to Nearest, ties to Max Magnitude - !101 ! !_Reserved for future use._ - !110 ! !_Reserved for future use._ - !111 !DYN !In instruction's _rm_ field, selects dynamic rounding mode; In Rounding Mode register, _reserved_. - !=== - - A value of 111 in the - instruction's _rm_ field selects the dynamic rounding mode held in - `frm`. The behavior of floating-point instructions that depend on - rounding mode when executed with a reserved rounding mode is _reserved_, - including both static reserved rounding modes (101-110) and dynamic reserved - rounding modes (101-111). Some instructions, including widening conversions, - have the _rm_ field but are nevertheless mathematically unaffected by the - rounding mode; software should set their _rm_ field to - RNE (000) but implementations must treat the _rm_ field as usual (in - particular, with regard to decoding legal vs. reserved encodings). + [[rm]] + .Rounding mode encoding. + [%autowidth,float="center",align="center",cols="^,^,<",options="header"] + !=== + !Rounding Mode |Mnemonic |Meaning + !000 !RNE !Round to Nearest, ties to Even + !001 !RTZ !Round towards Zero + !010 !RDN !Round Down (towards latexmath:[$-\infty$]) + !011 !RUP !Round Up (towards latexmath:[$+\infty$]) + !100 !RMM !Round to Nearest, ties to Max Magnitude + !101 ! !_Reserved for future use._ + !110 ! !_Reserved for future use._ + !111 !DYN !In instruction's _rm_ field, selects dynamic rounding mode; In Rounding Mode register, _reserved_. + !=== + - id: csr-frm-reserved + normative: false + text: | + The behavior of floating-point instructions that depend on rounding mode when + executed with a reserved rounding mode is _reserved_, including both static + reserved rounding modes (101-110) and dynamic reserved rounding modes (101-111). + - id: csr-frm-rmfield + normative: false + text: | + Some instructions, including widening conversions, have the _rm_ field but are + nevertheless mathematically unaffected by the rounding mode; software should set + their _rm_ field to RNE (000) but implementations must treat the _rm_ field as + usual (in particular, with regard to decoding legal vs. reserved encodings). priv_mode: U length: 32 From 368af3b60963e3fdbc022f0224289676641f531f Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Mon, 5 May 2025 15:23:58 +0000 Subject: [PATCH 7/7] add sw_write --- arch/csr/F/fflags.yaml | 15 +++++++++++++++ arch/csr/F/frm.yaml | 3 +++ 2 files changed, 18 insertions(+) diff --git a/arch/csr/F/fflags.yaml b/arch/csr/F/fflags.yaml index c310f23db..38cfb607d 100644 --- a/arch/csr/F/fflags.yaml +++ b/arch/csr/F/fflags.yaml @@ -35,6 +35,9 @@ fields: cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + CSR[fcsr].NV = csr_value.NV; + return csr_value.NV; DZ: alias: fcsr.DZ long_name: Divide by Zero @@ -44,6 +47,9 @@ fields: cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + CSR[fcsr].DZ = csr_value.DZ; + return csr_value.DZ; OF: alias: fcsr.OF long_name: Overflow @@ -53,6 +59,9 @@ fields: cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + CSR[fcsr].OF = csr_value.OF; + return csr_value.OF; UF: alias: fcsr.UF long_name: Underflow @@ -62,6 +71,9 @@ fields: cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + CSR[fcsr].UF = csr_value.UF; + return csr_value.UF; NX: alias: fcsr.NX long_name: Inexact @@ -71,6 +83,9 @@ fields: cleared by software. type: RW-H reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + CSR[fcsr].NX = csr_value.NX; + return csr_value.NX; sw_read(): | return (CSR[fcsr].NV `<< 4) | diff --git a/arch/csr/F/frm.yaml b/arch/csr/F/frm.yaml index 767996536..79bd092ff 100644 --- a/arch/csr/F/frm.yaml +++ b/arch/csr/F/frm.yaml @@ -50,6 +50,9 @@ fields: Rounding mode data. type: RW-H reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + CSR[fcsr].FRM = csr_value.ROUNDINGMODE; + return csr_value.ROUNDINGMODE; sw_read(): | return CSR[fcsr].FRM;