From 0e1a7fbb5287bbc544c87a91c4a4e063ef0886c3 Mon Sep 17 00:00:00 2001 From: ShehrozKashif Date: Wed, 16 Apr 2025 10:07:42 +0000 Subject: [PATCH 1/3] feat(csr): add H-mode CSRs vsip, hegeie, hideleg, hie, hip, hvip, vsie, vsscratch, hgeip --- arch/csr/H/hgeie.yaml | 30 ++++++++++++++++++ arch/csr/H/hgeip.yaml | 32 ++++++++++++++++++++ arch/csr/H/hideleg.yaml | 64 +++++++++++++++++++++++++++++++++++++++ arch/csr/H/hie.yaml | 46 ++++++++++++++++++++++++++++ arch/csr/H/hip.yaml | 46 ++++++++++++++++++++++++++++ arch/csr/H/hvip.yaml | 37 ++++++++++++++++++++++ arch/csr/H/vsie.yaml | 53 ++++++++++++++++++++++++++++++++ arch/csr/H/vsip.yaml | 64 +++++++++++++++++++++++++++++++++++++++ arch/csr/H/vsscratch.yaml | 17 +++++++++++ 9 files changed, 389 insertions(+) create mode 100644 arch/csr/H/hgeie.yaml create mode 100644 arch/csr/H/hgeip.yaml create mode 100644 arch/csr/H/hideleg.yaml create mode 100644 arch/csr/H/hie.yaml create mode 100644 arch/csr/H/hip.yaml create mode 100644 arch/csr/H/hvip.yaml create mode 100644 arch/csr/H/vsie.yaml create mode 100644 arch/csr/H/vsip.yaml create mode 100644 arch/csr/H/vsscratch.yaml diff --git a/arch/csr/H/hgeie.yaml b/arch/csr/H/hgeie.yaml new file mode 100644 index 000000000..42913bc3f --- /dev/null +++ b/arch/csr/H/hgeie.yaml @@ -0,0 +1,30 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hgeie +long_name: Hypervisor Guest External Interrupt Enable Register +description: | + The hgeie register is an HSXLEN-bit read/write register that contains enable bits for the guest external interrupts at this hart. Guest external interrupt number i corresponds with bit i in hgeie. + + Guest external interrupts represent interrupts directed to individual virtual machines at VS-level. If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine. + + [Note] + Support for guest external interrupts requires an interrupt controller that can collect virtual-machine-directed interrupts separately from other interrupts. + + The number of bits implemented in hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros. + + Register hgeie selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt. The enable bits in hgeie do not affect the VS-level external interrupt signal selected from hgeip by hstatus.VGEIN. +address: 0x607 +priv_mode: S +definedBy: H +length: SXLEN +fields: + GEI_ENABLE: + location_rv32: 31-1 + location_rv64: 63-1 + type: RW + reset_value: 0 + description: | + The number of bits implemented in hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in hgeie. + Register hgeie selects the subset of guest external interrupts that cause a supervisor-level (HS-level) guest external interrupt. The enable bits in hgeie do not affect the VS-level external interrupt signal selected from hgeip by hstatus.VGEIN. diff --git a/arch/csr/H/hgeip.yaml b/arch/csr/H/hgeip.yaml new file mode 100644 index 000000000..75a066522 --- /dev/null +++ b/arch/csr/H/hgeip.yaml @@ -0,0 +1,32 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hgeip +long_name: Hypervisor Guest External Interrupt Pending Register +description: | + The hgeip register is an HSXLEN-bit read-only register, formatted as that indicates pending guest external interrupts for this hart. + + Guest external interrupts represent interrupts directed to individual virtual machines at VS-level. + If a RISC-V platform supports placing a physical device under the direct control of a guest OS with minimal hypervisor intervention (known as pass-through or direct assignment between a virtual machine and the physical device), then, in such circumstance, interrupts from the device are intended for a specific virtual machine. + Each bit of hgeip summarizes all pending interrupts directed to one virtual hart, as collected and reported by an interrupt controller. To distinguish specific pending interrupts from multiple devices, software must query the interrupt controller. + + The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero. + This number is known as GEILEN. The least-significant bits are implemented first, apart from bit 0. Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in both hgeip and hgeie +address: 0xE12 +priv_mode: S +definedBy: H +length: SXLEN +fields: + GEI_PENDING: + location_rv32: 31-1 + location_rv64: 63-1 + type: RO + reset_value: 0 + description: | + Each bit of hgeip summarizes all pending interrupts directed to one virtual hart, as collected and reported by an interrupt controller. + To distinguish specific pending interrupts from multiple devices, software must query the interrupt controller. + + The number of bits implemented in hgeip and hgeie for guest external interrupts is UNSPECIFIED and may be zero. This number is known as GEILEN. + The least-significant bits are implemented first, apart from bit 0. + Hence, if GEILEN is nonzero, bits GEILEN:1 shall be writable in hgeie, and all other bit positions shall be read-only zeros in both hgeip and hgeie. diff --git a/arch/csr/H/hideleg.yaml b/arch/csr/H/hideleg.yaml new file mode 100644 index 000000000..d9cf5b7f6 --- /dev/null +++ b/arch/csr/H/hideleg.yaml @@ -0,0 +1,64 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hideleg +long_name: Hypervisor Interrupt Delegation Register +description: | + Register hideleg is an HSXLEN-bit read/write register. By default, all traps at any privilege level are handled in M-mode, though M-mode usually uses the medeleg and mideleg CSRs to delegate some traps to HS-mode. + The hedeleg and hideleg CSRs allow these traps to be further delegated to a VS-mode guest; their layout is the same as medeleg and mideleg. + An interrupt that has been delegated to HS-mode (using mideleg) is further delegated to VS-mode if the corresponding hideleg bit is set. + Among bits 15:0 of hideleg, bits 10, 6, and 2 (corresponding to the standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level interrupts) are read-only zeros. +address: 0x603 +priv_mode: S +definedBy: H +length: SXLEN +fields: + SSI: + location: 1 + type: RO + reset_value: 0 + long_name: Supervisor Software Interrupt + description: Supervisor Software Interrupt + + VSSI: + location: 2 + type: RW + reset_value: 0 + long_name: Virtual Supervisor Software Interrupt + description: Virtual Supervisor Software Interrupt + + STI: + location: 5 + type: RO + reset_value: 0 + long_name: Supervisor Timer Interrupt + description: Supervisor Timer Interrupt + + VSTI: + location: 6 + type: RW + reset_value: 0 + long_name: Virtual Supervisor Timer Interrupt + description: Virtual Supervisor Timer Interrupt + + SEI: + location: 9 + type: RO + reset_value: 0 + long_name: Supervisor External Interrupt + description: Supervisor External Interrupt + + VSEI: + location: 10 + type: RW + reset_value: 0 + long_name: Virtual Supervisor External Interrupt + description: Virtual Supervisor External Interrupt + + SGEI: + location: 12 + type: RW + reset_value: 0 + long_name: Supervisor Guest External Interrupt + description: Supervisor Guest External Interrupt diff --git a/arch/csr/H/hie.yaml b/arch/csr/H/hie.yaml new file mode 100644 index 000000000..a814479da --- /dev/null +++ b/arch/csr/H/hie.yaml @@ -0,0 +1,46 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hie +long_name: Hypervisor Interrupt Enable Register +description: | + The `hie` register is a read/write register in HS-mode that enables interrupts. + It corresponds to the enable bits for VS-level and hypervisor-specific interrupts, and supplements + the HS-level `sie` register. +address: 0x604 +priv_mode: S +definedBy: H +length: SXLEN +fields: + SGEIE: + location: 12 + type: RW-H + reset_value: 0 + description: | + Hypervisor guest external interrupt enable bit. When set, allows external interrupts to be delivered + to VS-mode based on the `hgeie` setting. + + VSEIE: + location: 10 + type: RW-H + reset_value: 0 + description: | + VS-level external interrupt enable bit. When set, allows external interrupts directed to VS-level + to be processed based on the configuration in `hvip` and other platform-specific sources. + + VSTIE: + location: 6 + type: RW-H + reset_value: 0 + description: | + VS-level timer interrupt enable bit. When set, allows VS-level timer interrupts to be processed + based on the `hvip` configuration and any platform-specific timer interrupts. + + VSSIE: + location: 2 + type: RW-H + reset_value: 0 + description: | + VS-level software interrupt enable bit. When set, allows software interrupts directed to VS-level + to be processed, based on the configuration in `hvip`. diff --git a/arch/csr/H/hip.yaml b/arch/csr/H/hip.yaml new file mode 100644 index 000000000..d84dfbaf2 --- /dev/null +++ b/arch/csr/H/hip.yaml @@ -0,0 +1,46 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hip +long_name: Hypervisor Interrupt Pending Register +description: | + The `hip` register is an HSXLEN-bit read/write register that indicates pending interrupts at the hypervisor level. + It contains interrupt-pending bits for both VS-level and hypervisor-specific interrupts. +address: 0x608 +priv_mode: S +definedBy: H +length: SXLEN +fields: + SGEIP: + location: 12 + type: RO + reset_value: 0 + description: | + Pending interrupt bit for supervisor guest external interrupts (SGEI). + This bit is 1 if and only if the logical AND of `hgeip` and `hgeie` is nonzero. + + VSEIP: + location: 10 + type: RO + reset_value: 0 + description: | + Pending interrupt bit for VS-level external interrupts (VSEI). + This bit is the logical OR of `vseip` from `hvip`, the interrupt from `hgeip` selected by `hstatus.VGEIN`, + and any other external interrupt signal directed to VS-level. + + VSTIP: + location: 6 + type: RO + reset_value: 0 + description: | + Pending interrupt bit for VS-level timer interrupts (VSTI). + This bit is the logical OR of `vstip` from `hvip` and any other timer interrupt directed to VS-level. + + VSSIP: + location: 2 + type: RO + reset_value: 0 + description: | + Pending interrupt bit for VS-level software interrupts (VSSI). + This bit is an alias of the `vssip` bit in `hvip`. diff --git a/arch/csr/H/hvip.yaml b/arch/csr/H/hvip.yaml new file mode 100644 index 000000000..a08b0bffe --- /dev/null +++ b/arch/csr/H/hvip.yaml @@ -0,0 +1,37 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hvip +long_name: Hypervisor Virtual Interrupt Pending Register +description: | + The `hvip` register is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode. + It contains interrupt-pending bits for virtual interrupts such as VS-level external interrupts, timer interrupts, and software interrupts. +address: 0x645 +priv_mode: S +definedBy: H +length: SXLEN +fields: + VSEIP: + location: 10 + type: RW + reset_value: 0 + description: | + Pending interrupt bit for VS-level external interrupts. This bit is writable and + is set to 1 to assert a VS-level external interrupt. + + VSTIP: + location: 6 + type: RW + reset_value: 0 + description: | + Pending interrupt bit for VS-level timer interrupts. This bit is writable and + is set to 1 to assert a VS-level timer interrupt. + + VSSIP: + location: 2 + type: RW + reset_value: 0 + description: | + Pending interrupt bit for VS-level software interrupts. This bit is writable and + is set to 1 to assert a VS-level software interrupt. diff --git a/arch/csr/H/vsie.yaml b/arch/csr/H/vsie.yaml new file mode 100644 index 000000000..c2161c087 --- /dev/null +++ b/arch/csr/H/vsie.yaml @@ -0,0 +1,53 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: vsie +address: 0x204 +virtual_address: 0x144 +long_name: Virtual Supervisor Interrupt Enable +description: | + The vsie register is a VSXLEN-bit read/write register that is VS-mode’s version of + supervisor CSR sie. When V=1, vsie substitutes for the usual sie, so instructions that + normally read or modify sie actually access vsie instead. However, interrupts directed to + HS-level continue to be indicated in the HS-level sip register, not in vsip, when V=1. + + When bit 13 of hideleg is zero, vsie.LCOFIE is read-only zero. Else, vsie.LCOFIE is an alias of sie.LCOFIE. + When bit 10 of hideleg is zero, vsie.SEIE is read-only zero. Else, vsie.SEIE is an alias of hie.VSEIE. + When bit 6 of hideleg is zero, vsie.STIE is read-only zero. Else, vsie.STIE is an alias of hie.VSTIE. + When bit 2 of hideleg is zero, vsie.SSIE is read-only zero. Else, vsie.SSIE is an alias of hie.VSSIE. +priv_mode: VS +definedBy: H +length: VSXLEN +fields: + SSIE: + location: 1 + type: RW-H + reset_value: UNDEFINED_LEGAL + alias: hie.VSSIE[0] + description: | + SSIE. Read-only zero when hideleg[2] is 0. Else, alias of hie.VSSIE. + + STIE: + location: 5 + type: RW-H + reset_value: UNDEFINED_LEGAL + alias: hie.VSTIE[0] + description: | + STIE. Read-only zero when hideleg[6] is 0. Else, alias of hie.VSTIE. + + SEIE: + location: 9 + type: RW-H + reset_value: UNDEFINED_LEGAL + alias: hie.VSEIE[0] + description: | + SEIE. Read-only zero when hideleg[10] is 0. Else, alias of hie.VSEIE. + + LCOFIE: + location: 13 + type: RW-H + reset_value: UNDEFINED_LEGAL + alias: sie.LCOFIE[0] + description: | + LCOFIE. Read-only zero when hideleg[13] is 0. Else, alias of sie.LCOFIE. diff --git a/arch/csr/H/vsip.yaml b/arch/csr/H/vsip.yaml new file mode 100644 index 000000000..34f516241 --- /dev/null +++ b/arch/csr/H/vsip.yaml @@ -0,0 +1,64 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: vsip +address: 0x244 +virtual_address: 0x144 +long_name: Virtual Supervisor Interrupt Pending +description: | + The `vsip` register is a VSXLEN-bit read/write register that is VS-mode’s version of the `sip` CSR. + When V=1, instructions that normally access `sip` instead access `vsip`. It holds the pending + interrupt status for supervisor-level traps in a virtualized environment. + + However, interrupts directed to HS-level continue to be indicated in the HS-level `sip` register, + not in `vsip`, when V=1. + + The standard portion (bits 15:0) includes individual interrupt-pending bits. +priv_mode: VS +definedBy: H +length: VSXLEN +fields: + SSIP: + location: 1 + type: RW-H + reset_value: UNDEFINED_LEGAL + alias: hip.VSSIP[0] + description: | + *Supervisor Software Interrupt Pending* + + Indicates a pending software interrupt at the supervisor level. + Read-only zero when `hideleg[2] == 0`, else aliased to `hip.VSSIP[0]`. + + STIP: + location: 5 + type: RW-H + reset_value: UNDEFINED_LEGAL + alias: hip.VSTIP[0] + description: | + *Supervisor Timer Interrupt Pending* + + Indicates a pending timer interrupt at the supervisor level. + Read-only zero when `hideleg[6] == 0`, else aliased to `hip.VSTIP[0]`. + + SEIP: + location: 9 + type: RW-H + reset_value: UNDEFINED_LEGAL + alias: hip.VSEIP[0] + description: | + *Supervisor External Interrupt Pending* + + Indicates a pending external interrupt at the supervisor level. + Read-only zero when `hideleg[10] == 0`, else aliased to `hip.VSEIP[0]`. + + LCOFIP: + location: 13 + type: RW-H + reset_value: UNDEFINED_LEGAL + alias: sip.LCOFIP[0] + description: | + *Local Counter Overflow Interrupt Pending* + + Indicates an overflow of a local counter. + Read-only zero when `hideleg[13] == 0`, else aliased to `sip.LCOFIP[0]`. diff --git a/arch/csr/H/vsscratch.yaml b/arch/csr/H/vsscratch.yaml new file mode 100644 index 000000000..ef81a1ded --- /dev/null +++ b/arch/csr/H/vsscratch.yaml @@ -0,0 +1,17 @@ +# yaml-language-server: $schema=../../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: vsscratch +address: 0x240 +virtual_address: 0x140 +long_name: Virtual Supervisor Scratch Register +description: | + The vsscratch register is a VSXLEN-bit read/write register that is VS-mode’s version of + supervisor register sscratch. When V=1, vsscratch substitutes for the usual sscratch, + so instructions that normally read or modify sscratch actually access vsscratch instead. + The contents of vsscratch never directly affect the behavior of the machine. +priv_mode: VS +length: VSXLEN +definedBy: H +fields: {} From 78cda11a378b630e93fef0d7456669ee2f160814 Mon Sep 17 00:00:00 2001 From: Shehroz Kashif <131602772+Shehrozkashif@users.noreply.github.com> Date: Tue, 3 Jun 2025 12:58:32 +0500 Subject: [PATCH 2/3] Update arch/csr/H/vsscratch.yaml Co-authored-by: Paul Clarke Signed-off-by: Shehroz Kashif <131602772+Shehrozkashif@users.noreply.github.com> --- arch/csr/H/vsscratch.yaml | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-) diff --git a/arch/csr/H/vsscratch.yaml b/arch/csr/H/vsscratch.yaml index 730f208d3..3a278e2bb 100644 --- a/arch/csr/H/vsscratch.yaml +++ b/arch/csr/H/vsscratch.yaml @@ -25,6 +25,7 @@ fields: SCRATCH: type: RW reset_value: 0 - location: 0 + location_rv32: 31-0 + location_rv64: 63-0 description: | Virtual supervisor scratch register. From 1643f21381af11f160668b1547bba4297dd36382 Mon Sep 17 00:00:00 2001 From: ShehrozKashif Date: Fri, 6 Jun 2025 20:54:34 +0000 Subject: [PATCH 3/3] feat(cpu): add Sstc CSRs --- arch/csr/stimecmp.yaml | 58 +++++++++++++++++++++++++++++++++++++++++ arch/csr/vstimecmp.yaml | 56 +++++++++++++++++++++++++++++++++++++++ 2 files changed, 114 insertions(+) create mode 100644 arch/csr/stimecmp.yaml create mode 100644 arch/csr/vstimecmp.yaml diff --git a/arch/csr/stimecmp.yaml b/arch/csr/stimecmp.yaml new file mode 100644 index 000000000..9bf96014f --- /dev/null +++ b/arch/csr/stimecmp.yaml @@ -0,0 +1,58 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: stimecmp +long_name: Supervisor Timer Compare Register +virtual_address: 0x14D +address: 0x14D +priv_mode: S +definedBy: Sstc +length: 64 + +description: + - id: csr-stimecmp-purpose + normative: true + text: | + The stimecmp CSR is a 64-bit register and provides 64-bit precision on all RV32 and RV64 systems. + On RV32, accesses to the stimecmp CSR access the low 32 bits, while accesses to the stimecmph CSR + access the high 32 bits of stimecmp. + The CSR numbers for stimecmp and stimecmph are 0x14D and 0x15D, respectively, within the Supervisor Trap Setup block. + + - id: csr-stimecmp-interrupt + normative: true + text: | + A supervisor timer interrupt becomes pending, as reflected in the STIP bit in the mip and sip registers, + whenever the time register contains a value greater than or equal to stimecmp, treating the values as unsigned integers. + If the result of this comparison changes, it is guaranteed to be reflected in STIP eventually, + but not necessarily immediately. + The interrupt remains posted until stimecmp becomes greater than time, typically due to writing a new value to stimecmp. + The interrupt is taken based on standard interrupt enable and delegation rules. + + - id: csr-stimecmp-spurious + normative: false + text: | + A spurious timer interrupt might occur if an interrupt handler advances stimecmp and immediately returns, + because STIP might not yet have fallen. All software should be written to account for this possibility, + although it is generally rare. It is usually more efficient to tolerate occasional spurious timer interrupts + than to poll STIP until it clears. + + - id: csr-stimecmp-sbi + normative: false + text: | + In systems where a Supervisor Execution Environment (SEE) provides timer services via an SBI call, + the SBI will continue to support scheduling timer interrupts. The SEE updates stimecmp as needed. + This ensures compatibility with existing S-mode software, while newer software can interact with stimecmp directly. + +fields: + STIMECMP: + long_name: Supervisor timer compare value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + reset_value: 0 + sw_write(csr_value): | + return csr_value.STIMECMP; + description: | + The value in stimecmp is compared against the current value of the time CSR. + If time is greater than or equal to stimecmp, a supervisor timer interrupt (STIP) is posted. diff --git a/arch/csr/vstimecmp.yaml b/arch/csr/vstimecmp.yaml new file mode 100644 index 000000000..4383ccb87 --- /dev/null +++ b/arch/csr/vstimecmp.yaml @@ -0,0 +1,56 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: vstimecmp +long_name: Virtual Supervisor Timer Register +virtual_address: 0x24D +address: 0x24D +priv_mode: VS +definedBy: H +length: SXLEN + +description: + - id: csr-vstimecmp-purpose + normative: true + text: | + The vstimecmp CSR is a 64-bit register and has 64-bit precision on all RV32 and RV64 systems. + In RV32 only, accesses to the vstimecmp CSR access the low 32 bits, while accesses to the vstimecmph CSR + access the high 32 bits of vstimecmp. + + - id: csr-vstimecmp-csr-numbers + normative: true + text: | + The proposed CSR numbers for vstimecmp / vstimecmph are 0x24D / 0x25D (within the Virtual Supervisor + Registers block of CSRs, and mirroring the CSR numbers for stimecmp/stimecmph). + + - id: csr-vstimecmp-interrupt + normative: true + text: | + A virtual supervisor timer interrupt becomes pending, as reflected in the VSTIP bit in the hip register, + whenever (time + htimedelta), truncated to 64 bits, contains a value greater than or equal to vstimecmp, + treating the values as unsigned integers. + If the result of this comparison changes, it is guaranteed to be reflected in VSTIP eventually, but not necessarily immediately. + The interrupt remains posted until vstimecmp becomes greater than (time + htimedelta), typically as a result of writing vstimecmp. + The interrupt will be taken based on the standard interrupt enable and delegation rules while V=1. + + - id: csr-vstimecmp-compat + normative: false + text: | + In systems in which a supervisor execution environment (SEE) implemented by an + HS-mode hypervisor provides timer facilities via an SBI function call, this SBI call will + continue to support requests to schedule a timer interrupt. The SEE will simply make + use of vstimecmp, changing its value as appropriate. This ensures compatibility with + existing guest VS-mode software that uses this SEE facility, while new VS-mode + software takes advantage of vstimecmp directly. + +fields: + VSTIMECMP: + long_name: Virtual supervisor timer compare value + location_rv32: 31-0 + location_rv64: 63-0 + type: RW + reset_value: UNDEFINED_LEGAL + description: | + The value in vstimecmp is compared with (time + htimedelta), truncated to 64 bits, + to determine whether a virtual supervisor timer interrupt should be posted in VSTIP.