From 6a3c81c58501a7505849edb998684b55d5332674 Mon Sep 17 00:00:00 2001 From: Katherine <2katherinehsu@gmail.com> Date: Fri, 4 Apr 2025 02:05:47 +0000 Subject: [PATCH 01/38] add smstateen/ssstateen CSRs --- arch/csr/hstateen0.yaml | 100 +++++++++++++++++++++++++++++++++++++++ arch/csr/hstateen0h.yaml | 70 +++++++++++++++++++++++++++ arch/csr/hstateen1.yaml | 34 +++++++++++++ arch/csr/hstateen1h.yaml | 31 ++++++++++++ arch/csr/hstateen2.yaml | 34 +++++++++++++ arch/csr/hstateen2h.yaml | 31 ++++++++++++ arch/csr/hstateen3.yaml | 34 +++++++++++++ arch/csr/hstateen3h.yaml | 31 ++++++++++++ arch/csr/mstateen0.yaml | 95 +++++++++++++++++++++++++++++++++++++ arch/csr/mstateen0h.yaml | 63 ++++++++++++++++++++++++ arch/csr/mstateen1.yaml | 27 +++++++++++ arch/csr/mstateen1h.yaml | 22 +++++++++ arch/csr/mstateen2.yaml | 27 +++++++++++ arch/csr/mstateen2h.yaml | 22 +++++++++ arch/csr/mstateen3.yaml | 27 +++++++++++ arch/csr/mstateen3h.yaml | 22 +++++++++ arch/csr/sstateen0.yaml | 71 +++++++++++++++++++++++++++ arch/csr/sstateen1.yaml | 50 ++++++++++++++++++++ arch/csr/sstateen2.yaml | 50 ++++++++++++++++++++ arch/csr/sstateen3.yaml | 50 ++++++++++++++++++++ arch/ext/Smstateen.yaml | 25 ++++++++++ 21 files changed, 916 insertions(+) create mode 100644 arch/csr/hstateen0.yaml create mode 100644 arch/csr/hstateen0h.yaml create mode 100644 arch/csr/hstateen1.yaml create mode 100644 arch/csr/hstateen1h.yaml create mode 100644 arch/csr/hstateen2.yaml create mode 100644 arch/csr/hstateen2h.yaml create mode 100644 arch/csr/hstateen3.yaml create mode 100644 arch/csr/hstateen3h.yaml create mode 100644 arch/csr/mstateen0.yaml create mode 100644 arch/csr/mstateen0h.yaml create mode 100644 arch/csr/mstateen1.yaml create mode 100644 arch/csr/mstateen1h.yaml create mode 100644 arch/csr/mstateen2.yaml create mode 100644 arch/csr/mstateen2h.yaml create mode 100644 arch/csr/mstateen3.yaml create mode 100644 arch/csr/mstateen3h.yaml create mode 100644 arch/csr/sstateen0.yaml create mode 100644 arch/csr/sstateen1.yaml create mode 100644 arch/csr/sstateen2.yaml create mode 100644 arch/csr/sstateen3.yaml create mode 100644 arch/ext/Smstateen.yaml diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml new file mode 100644 index 000000000..baa4028d5 --- /dev/null +++ b/arch/csr/hstateen0.yaml @@ -0,0 +1,100 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hstateen0 +long_name: Hypervisor State Enable 0 Register +address: 0x60C +priv_mode: S +length: 64 +description: | + For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. + Bit 63 of hstateen0 controls access to sstateen0. + + With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen + CSRs, except controlling accesses for a virtual machine (from VS and VU modes). + + For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in sstateen when accessed in VS-mode. + + A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one + in the matching mstateen CSR. + +definedBy: + allOf: + - H + - Smstateen + - Ssstateen +fields: + SEO: + location: 63 + description: | + The SE0 bit in hstateen0 controls access to the sstateen0 CSR. + type: RW + reset_value: UNDEFINED_LEGAL + ENVCFG: + location: 62 + description: | + The ENVCFG bit in hstateen0 controls access to the senvcfg CSRs. + type: RW + reset_value: UNDEFINED_LEGAL + CSRIND: + location: 60 + description: | + The CSRIND bit in hstateen0 controls access to the siselect and the + sireg*, (really vsiselect and vsireg*) CSRs provided by the Sscsrind + extensions. + type: RW + reset_value: UNDEFINED_LEGAL + AIA: + location: 59 + description: | + The AIA bit in hstateen0 controls access to all state introduced by + the Ssaia extension and is not controlled by either the CSRIND or the + IMSIC bits of hstateen0. + type: RW + reset_value: UNDEFINED_LEGAL + IMSIC: + location: 58 + description: | + The IMSIC bit in hstateen0 controls access to the guest IMSIC state, + including CSRs stopei (really vstopei), provided by the Ssaia extension. + + Setting the IMSIC bit in hstateen0 to zero prevents a virtual machine + from accessing the hart’s IMSIC the same as setting `hstatus.`VGEIN = 0. + type: RW + reset_value: UNDEFINED_LEGAL + CONTEXT: + location: 57 + description: | + The CONTEXT bit in hstateen0 controls access to the scontext CSR provided + by the Sdtrig extension. + type: RW + reset_value: UNDEFINED_LEGAL + JVT: + location: 2 + description: | + The JVT bit controls access to the jvt CSR provided by the Zcmt extension. + type: RW + reset_value: UNDEFINED_LEGAL + FCSR: + location: 1 + description: | + The FCSR bit controls access to fcsr for the case when floating-point instructions + operate on x registers instead of f registers as specified by the Zfinx and related + extensions (Zdinx, etc.). Whenever misa.F = 1, FCSR bit of mstateen0 is read-only + zero (and hence read-only zero in hstateen0 and sstateen0 too). For convenience, + when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a + controlling stateen0 CSR is zero, all floating-point instructions cause an illegal + instruction trap (or virtual instruction trap, if relevant), as though they all access + fcsr, regardless of whether they really do. + type: RW + reset_value: UNDEFINED_LEGAL + C: + location: 0 + description: | + The C bit controls access to any and all custom state. This bit is not custom state itself. + The C bit of these registers is not custom state itself; it is a standard field of a + standard CSR, either mstateen0, hstateen0, or sstateen0. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen0h.yaml b/arch/csr/hstateen0h.yaml new file mode 100644 index 000000000..9a7cb17dc --- /dev/null +++ b/arch/csr/hstateen0h.yaml @@ -0,0 +1,70 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hstateen0h +long_name: Upper 32 bits of Hypervisor State Enable 0 Register +address: 0x61C +priv_mode: S +length: 32 +description: | + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), + mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented, + another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3. + + For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding + set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, + hstateen1h, hstateen2h, and hstateen3h. + +definedBy: + allOf: + - H + - Smstateen + - Ssstateen +fields: + SEO: + location: 31 + description: | + The SE0 bit in hstateen0h controls access to the sstateen0 CSR. + type: RW + reset_value: UNDEFINED_LEGAL + ENVCFG: + location: 30 + description: | + The ENVCFG bit in hstateen0h controls access to the senvcfg CSRs. + type: RW + reset_value: UNDEFINED_LEGAL + CSRIND: + location: 28 + description: | + The CSRIND bit in hstateen0h controls access to the siselect and the + sireg*, (really vsiselect and vsireg*) CSRs provided by the Sscsrind + extensions. + type: RW + reset_value: UNDEFINED_LEGAL + AIA: + location: 27 + description: | + The AIA bit in hstateen0h controls access to all state introduced by + the Ssaia extension and is not controlled by either the CSRIND or the + IMSIC bits of hstateen0. + type: RW + reset_value: UNDEFINED_LEGAL + IMSIC: + location: 26 + description: | + The IMSIC bit in hstateen0h controls access to the guest IMSIC state, + including CSRs stopei (really vstopei), provided by the Ssaia extension. + + Setting the IMSIC bit in hstateen0h to zero prevents a virtual machine + from accessing the hart’s IMSIC the same as setting `hstatus.`VGEIN = 0. + type: RW + reset_value: UNDEFINED_LEGAL + CONTEXT: + location: 25 + description: | + The CONTEXT bit in hstateen0h controls access to the scontext CSR provided + by the Sdtrig extension. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml new file mode 100644 index 000000000..f88616275 --- /dev/null +++ b/arch/csr/hstateen1.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hstateen1 +long_name: Hypervisor State Enable 1 Register +address: 0x60D +priv_mode: S +length: 64 +description: | + For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. + Bit 63 of hstateen1 controls access to sstateen1. + + With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen + CSRs, except controlling accesses for a virtual machine (from VS and VU modes). + + For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in sstateen when accessed in VS-mode. + + A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one + in the matching mstateen CSR. + +definedBy: + allOf: + - H + - Smstateen + - Ssstateen +fields: + SEO: + location: 63 + description: | + The SE0 bit in hstateen1 controls access to the sstateen1 CSR. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen1h.yaml b/arch/csr/hstateen1h.yaml new file mode 100644 index 000000000..207d926cb --- /dev/null +++ b/arch/csr/hstateen1h.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hstateen1h +long_name: Upper 32 bits of Hypervisor State Enable 1 Register +address: 0x61D +priv_mode: S +length: 32 +description: | + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), + mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented, + another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3. + + For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding + set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, + hstateen1h, hstateen2h, and hstateen3h. + +definedBy: + allOf: + - H + - Smstateen + - Ssstateen +fields: + SEO: + location: 31 + description: | + The SE0 bit in hstateen1h controls access to the sstateen1 CSR. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml new file mode 100644 index 000000000..af6137b93 --- /dev/null +++ b/arch/csr/hstateen2.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hstateen2 +long_name: Hypervisor State Enable 2 Register +address: 0x60E +priv_mode: S +length: 64 +description: | + For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. + Bit 63 of hstateen2 controls access to sstateen2. + + With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen + CSRs, except controlling accesses for a virtual machine (from VS and VU modes). + + For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in sstateen when accessed in VS-mode. + + A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one + in the matching mstateen CSR. + +definedBy: + allOf: + - H + - Smstateen + - Ssstateen +fields: + SEO: + location: 63 + description: | + The SE0 bit in hstateen2 controls access to the sstateen2 CSR. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen2h.yaml b/arch/csr/hstateen2h.yaml new file mode 100644 index 000000000..b1bd9861b --- /dev/null +++ b/arch/csr/hstateen2h.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hstateen2h +long_name: Upper 32 bits of Hypervisor State Enable 2 Register +address: 0x61E +priv_mode: S +length: 32 +description: | + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), + mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented, + another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3. + + For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding + set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, + hstateen1h, hstateen2h, and hstateen3h. + +definedBy: + allOf: + - H + - Smstateen + - Ssstateen +fields: + SEO: + location: 31 + description: | + The SE0 bit in hstateen2h controls access to the sstateen2 CSR. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml new file mode 100644 index 000000000..3d7f8bf88 --- /dev/null +++ b/arch/csr/hstateen3.yaml @@ -0,0 +1,34 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hstateen3 +long_name: Hypervisor State Enable 3 Register +address: 0x60F +priv_mode: S +length: 64 +description: | + For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. + Bit 63 of hstateen3 controls access to sstateen3. + + With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen + CSRs, except controlling accesses for a virtual machine (from VS and VU modes). + + For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in sstateen when accessed in VS-mode. + + A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one + in the matching mstateen CSR. + +definedBy: + allOf: + - H + - Smstateen + - Ssstateen +fields: + SEO: + location: 63 + description: | + The SE0 bit in hstateen3 controls access to the sstateen3 CSR. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen3h.yaml b/arch/csr/hstateen3h.yaml new file mode 100644 index 000000000..738a16ed7 --- /dev/null +++ b/arch/csr/hstateen3h.yaml @@ -0,0 +1,31 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: hstateen3h +long_name: Upper 32 bits of Hypervisor State Enable 3 Register +address: 0x61F +priv_mode: S +length: 32 +description: | + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), + mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented, + another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3. + + For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding + set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, + hstateen1h, hstateen2h, and hstateen3h. + +definedBy: + allOf: + - H + - Smstateen + - Ssstateen +fields: + SEO: + location: 31 + description: | + The SE0 bit in hstateen3h controls access to the sstateen3 CSR. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml new file mode 100644 index 000000000..c846428ae --- /dev/null +++ b/arch/csr/mstateen0.yaml @@ -0,0 +1,95 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: mstateen0 +long_name: Machine State Enable 0 Register +address: 0x30C +priv_mode: M +length: 64 +description: | + For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen + CSRs. Bit 63 of mstateen0 controls access to sstateen0 and hstateen0. + + On reset, all writable mstateen bits are initialized by the hardware to zeros. If machine-level software + changes these values, it is responsible for initializing the corresponding writable bits of the hstateen + and sstateen CSRs to zeros too. Software at each privilege level should set its respective stateen CSRs + to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, + this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to + manage in some other way. +definedBy: Smstateen +fields: + SEO: + location: 63 + description: | + The SE0 bit in mstateen0 controls access to the hstateen0, hstateen0h, and the sstateen0 CSRs. + type: RW + reset_value: UNDEFINED_LEGAL + ENVCFG: + location: 62 + description: | + The ENVCFG bit in mstateen0 controls access to the henvcfg, henvcfgh, and the senvcfg CSRs. + type: RW + reset_value: UNDEFINED_LEGAL + CSRIND: + location: 60 + description: | + The CSRIND bit in mstateen0 controls access to the siselect, sireg*, vsiselect, and the vsireg* + CSRs provided by the Sscsrind extensions. + type: RW + reset_value: UNDEFINED_LEGAL + AIA: + location: 59 + description: | + The AIA bit in mstateen0 controls access to all state introduced by the Ssaia extension and is not + controlled by either the CSRIND or the IMSIC bits. + type: RW + reset_value: UNDEFINED_LEGAL + IMSIC: + location: 58 + description: | + The IMSIC bit in mstateen0 controls access to the IMSIC state, including CSRs stopei and vstopei, + provided by the Ssaia extension. + type: RW + reset_value: UNDEFINED_LEGAL + CONTEXT: + location: 57 + description: | + The CONTEXT bit in mstateen0 controls access to the scontext and hcontext CSRs provided by the + Sdtrig extension. + type: RW + reset_value: UNDEFINED_LEGAL + P1P13: + location: 56 + description: | + The P1P13 bit in mstateen0 controls access to the hedelegh introduced by Privileged Specification + Version 1.13. + type: RW + reset_value: UNDEFINED_LEGAL + JVT: + location: 2 + description: | + The JVT bit controls access to the jvt CSR provided by the Zcmt extension. + type: RW + reset_value: UNDEFINED_LEGAL + FCSR: + location: 1 + description: | + The FCSR bit controls access to fcsr for the case when floating-point instructions + operate on x registers instead of f registers as specified by the Zfinx and related + extensions (Zdinx, etc.). Whenever misa.F = 1, FCSR bit of mstateen0 is read-only + zero (and hence read-only zero in hstateen0 and sstateen0 too). For convenience, + when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a + controlling stateen0 CSR is zero, all floating-point instructions cause an illegal + instruction trap (or virtual instruction trap, if relevant), as though they all access + fcsr, regardless of whether they really do. + type: RW + reset_value: UNDEFINED_LEGAL + C: + location: 0 + description: | + The C bit controls access to any and all custom state. This bit is not custom state itself. The C bit of + these registers is not custom state itself; it is a standard field of a standard CSR, either mstateen0, + hstateen0, or sstateen0. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml new file mode 100644 index 000000000..b6f31f877 --- /dev/null +++ b/arch/csr/mstateen0h.yaml @@ -0,0 +1,63 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: mstateen0h +long_name: Upper 32 bits of Machine State Enable 0 Register +address: 0x31C +priv_mode: M +length: 32 +description: | + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State + Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the + machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: + mstateen0h, mstateen1h, mstateen2h, mstateen3h. +definedBy: Smstateen +fields: + SEO: + location: 31 + description: | + The SE0 bit in mstateen0h controls access to the hstateen0, hstateen0h, and the sstateen0 CSRs. + type: RW + reset_value: UNDEFINED_LEGAL + ENVCFG: + location: 30 + description: | + The ENVCFG bit in mstateen0h controls access to the henvcfg, henvcfgh, and the senvcfg CSRs. + type: RW + reset_value: UNDEFINED_LEGAL + CSRIND: + location: 28 + description: | + The CSRIND bit in mstateen0h controls access to the siselect, sireg*, vsiselect, and the vsireg* + CSRs provided by the Sscsrind extensions. + type: RW + reset_value: UNDEFINED_LEGAL + AIA: + location: 27 + description: | + The AIA bit in mstateen0h controls access to all state introduced by the Ssaia extension and is not + controlled by either the CSRIND or the IMSIC bits. + type: RW + reset_value: UNDEFINED_LEGAL + IMSIC: + location: 26 + description: | + The IMSIC bit in mstateen0h controls access to the IMSIC state, including CSRs stopei and vstopei, + provided by the Ssaia extension. + type: RW + reset_value: UNDEFINED_LEGAL + CONTEXT: + location: 25 + description: | + The CONTEXT bit in mstateen0h controls access to the scontext and hcontext CSRs provided by the + Sdtrig extension. + type: RW + reset_value: UNDEFINED_LEGAL + P1P13: + location: 24 + description: | + The P1P13 bit in mstateen0h controls access to the hedelegh introduced by Privileged Specification + Version 1.13. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen1.yaml b/arch/csr/mstateen1.yaml new file mode 100644 index 000000000..778999636 --- /dev/null +++ b/arch/csr/mstateen1.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: mstateen1 +long_name: Machine State Enable 1 Register +address: 0x30D +priv_mode: M +length: 64 +description: | + For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen + CSRs. Bit 63 of mstateen1 controls access to sstateen1 and hstateen1. + + On reset, all writable mstateen bits are initialized by the hardware to zeros. If machine-level software + changes these values, it is responsible for initializing the corresponding writable bits of the hstateen + and sstateen CSRs to zeros too. Software at each privilege level should set its respective stateen CSRs + to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, + this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to + manage in some other way. +definedBy: Smstateen +fields: + SEO: + location: 63 + description: | + The SE0 bit in mstateen1 controls access to the hstateen1, hstateen1h, and the sstateen1 CSRs. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen1h.yaml b/arch/csr/mstateen1h.yaml new file mode 100644 index 000000000..d3720de4e --- /dev/null +++ b/arch/csr/mstateen1h.yaml @@ -0,0 +1,22 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: mstateen1h +long_name: Upper 32 bits of Machine State Enable 1 Register +address: 0x31D +priv_mode: M +length: 32 +description: | + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State + Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the + machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: + mstateen0h, mstateen1h, mstateen2h, mstateen3h. +definedBy: Smstateen +fields: + SEO: + location: 31 + description: | + The SE0 bit in mstateen1h controls access to the hstateen1, hstateen1h, and the sstateen1 CSRs. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen2.yaml b/arch/csr/mstateen2.yaml new file mode 100644 index 000000000..7415ed910 --- /dev/null +++ b/arch/csr/mstateen2.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: mstateen2 +long_name: Machine State Enable 2 Register +address: 0x30E +priv_mode: M +length: 64 +description: | + For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen + CSRs. Bit 63 of mstateen2 controls access to sstateen2 and hstateen2. + + On reset, all writable mstateen bits are initialized by the hardware to zeros. If machine-level software + changes these values, it is responsible for initializing the corresponding writable bits of the hstateen + and sstateen CSRs to zeros too. Software at each privilege level should set its respective stateen CSRs + to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, + this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to + manage in some other way. +definedBy: Smstateen +fields: + SEO: + location: 63 + description: | + The SE0 bit in mstateen2 controls access to the hstateen2, hstateen2h, and the sstateen2 CSRs. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen2h.yaml b/arch/csr/mstateen2h.yaml new file mode 100644 index 000000000..3c047c9fe --- /dev/null +++ b/arch/csr/mstateen2h.yaml @@ -0,0 +1,22 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: mstateen2h +long_name: Upper 32 bits of Machine State Enable 2 Register +address: 0x31E +priv_mode: M +length: 32 +description: | + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State + Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the + machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: + mstateen0h, mstateen1h, mstateen2h, mstateen3h. +definedBy: Smstateen +fields: + SEO: + location: 31 + description: | + The SE0 bit in mstateen2h controls access to the hstateen2, hstateen2h, and the sstateen2 CSRs. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen3.yaml b/arch/csr/mstateen3.yaml new file mode 100644 index 000000000..e77da9966 --- /dev/null +++ b/arch/csr/mstateen3.yaml @@ -0,0 +1,27 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: mstateen3 +long_name: Machine State Enable 3 Register +address: 0x30F +priv_mode: M +length: 64 +description: | + For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen + CSRs. Bit 63 of mstateen3 controls access to sstateen3 and hstateen3. + + On reset, all writable mstateen bits are initialized by the hardware to zeros. If machine-level software + changes these values, it is responsible for initializing the corresponding writable bits of the hstateen + and sstateen CSRs to zeros too. Software at each privilege level should set its respective stateen CSRs + to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, + this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to + manage in some other way. +definedBy: Smstateen +fields: + SEO: + location: 63 + description: | + The SE0 bit in mstateen3 controls access to the hstateen3, hstateen3h, and the sstateen3 CSRs. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen3h.yaml b/arch/csr/mstateen3h.yaml new file mode 100644 index 000000000..618be0379 --- /dev/null +++ b/arch/csr/mstateen3h.yaml @@ -0,0 +1,22 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: mstateen3h +long_name: Upper 32 bits of Machine State Enable 3 Register +address: 0x31F +priv_mode: M +length: 32 +description: | + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State + Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the + machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: + mstateen0h, mstateen1h, mstateen2h, mstateen3h. +definedBy: Smstateen +fields: + SEO: + location: 31 + description: | + The SE0 bit in mstateen3h controls access to the hstateen3, hstateen3h, and the sstateen3 CSRs. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml new file mode 100644 index 000000000..061bad084 --- /dev/null +++ b/arch/csr/sstateen0.yaml @@ -0,0 +1,71 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: sstateen0 +long_name: Supervisor State Enable 0 Register +address: 0x10C +priv_mode: S +length: 64 +description: | + For the supervisor-level sstateen registers, high-half CSRs are not added at this + time because it is expected the upper 32 bits of these registers will always be zeros. + + For every bit with a defined purpose in an sstateen CSR, the same bit is defined in the + matching mstateen CSR to control access below machine level to the same state. + + Each bit of a stateen CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in sstatus like the + FS and VS fields for the F and V extensions. The number of registers provided at each + level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor + levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to + come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an + attempted compromise between providing too few bits on the one hand and going overboard + with CSRs that will never be used on the other. + + The stateen registers at each level control access to state at all less-privileged levels, + but not at its own level. + + When a stateen CSR prevents access to state for a privilege mode, attempting to execute in + that privilege mode an instruction that implicitly updates the state without reading it may + or may not raise an illegal instruction or virtual instruction exception. Such cases must + be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the ISA + extensions that introduce the controlled state. + Each bit of a supervisor-level sstateen CSR controls user-level access (from U-mode or VU-mode) + to an extension’s state. The intention is to allocate the bits of sstateen CSRs starting at the + least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered + sstateen CSR. + +definedBy: + allOf: + - Smstateen + - Ssstateen +fields: + JVT: + location: 2 + description: | + The JVT bit controls access to the jvt CSR provided by the Zcmt extension. + type: RW + reset_value: UNDEFINED_LEGAL + FCSR: + location: 1 + description: | + The FCSR bit controls access to fcsr for the case when floating-point instructions + operate on x registers instead of f registers as specified by the Zfinx and related + extensions (Zdinx, etc.). Whenever misa.F = 1, FCSR bit of mstateen0 is read-only + zero (and hence read-only zero in hstateen0 and sstateen0 too). For convenience, + when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a + controlling stateen0 CSR is zero, all floating-point instructions cause an illegal + instruction trap (or virtual instruction trap, if relevant), as though they all access + fcsr, regardless of whether they really do. + type: RW + reset_value: UNDEFINED_LEGAL + C: + location: 0 + description: | + The C bit controls access to any and all custom state. This bit is not custom state itself. The C bit of + these registers is not custom state itself; it is a standard field of a standard CSR, either mstateen0, + hstateen0, or sstateen0. + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml new file mode 100644 index 000000000..67d98552f --- /dev/null +++ b/arch/csr/sstateen1.yaml @@ -0,0 +1,50 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: sstateen1 +long_name: Supervisor State Enable 1 Register +address: 0x10D +priv_mode: S +length: 64 +description: | + For the supervisor-level sstateen registers, high-half CSRs are not added at this + time because it is expected the upper 32 bits of these registers will always be zeros. + + For every bit with a defined purpose in an sstateen CSR, the same bit is defined in the + matching mstateen CSR to control access below machine level to the same state. + + Each bit of a stateen CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in sstatus like the + FS and VS fields for the F and V extensions. The number of registers provided at each + level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor + levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to + come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an + attempted compromise between providing too few bits on the one hand and going overboard + with CSRs that will never be used on the other. + + The stateen registers at each level control access to state at all less-privileged levels, + but not at its own level. + + When a stateen CSR prevents access to state for a privilege mode, attempting to execute in + that privilege mode an instruction that implicitly updates the state without reading it may + or may not raise an illegal instruction or virtual instruction exception. Such cases must + be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the ISA + extensions that introduce the controlled state. + Each bit of a supervisor-level sstateen CSR controls user-level access (from U-mode or VU-mode) + to an extension’s state. The intention is to allocate the bits of sstateen CSRs starting at the + least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered + sstateen CSR. + +definedBy: + allOf: + - Smstateen + - Ssstateen + +fields: + DATA: + location: 63-0 + description: Data value + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml new file mode 100644 index 000000000..69e26e930 --- /dev/null +++ b/arch/csr/sstateen2.yaml @@ -0,0 +1,50 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: sstateen2 +long_name: Supervisor State Enable 2 Register +address: 0x10E +priv_mode: S +length: 64 +description: | + For the supervisor-level sstateen registers, high-half CSRs are not added at this + time because it is expected the upper 32 bits of these registers will always be zeros. + + For every bit with a defined purpose in an sstateen CSR, the same bit is defined in the + matching mstateen CSR to control access below machine level to the same state. + + Each bit of a stateen CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in sstatus like the + FS and VS fields for the F and V extensions. The number of registers provided at each + level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor + levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to + come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an + attempted compromise between providing too few bits on the one hand and going overboard + with CSRs that will never be used on the other. + + The stateen registers at each level control access to state at all less-privileged levels, + but not at its own level. + + When a stateen CSR prevents access to state for a privilege mode, attempting to execute in + that privilege mode an instruction that implicitly updates the state without reading it may + or may not raise an illegal instruction or virtual instruction exception. Such cases must + be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the ISA + extensions that introduce the controlled state. + Each bit of a supervisor-level sstateen CSR controls user-level access (from U-mode or VU-mode) + to an extension’s state. The intention is to allocate the bits of sstateen CSRs starting at the + least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered + sstateen CSR. + +definedBy: + allOf: + - Smstateen + - Ssstateen + +fields: + DATA: + location: 63-0 + description: Data value + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml new file mode 100644 index 000000000..02ebe5905 --- /dev/null +++ b/arch/csr/sstateen3.yaml @@ -0,0 +1,50 @@ +# yaml-language-server: $schema=../../schemas/csr_schema.json + +$schema: "csr_schema.json#" +kind: csr +name: sstateen3 +long_name: Supervisor State Enable 3 Register +address: 0x10F +priv_mode: S +length: 64 +description: | + For the supervisor-level sstateen registers, high-half CSRs are not added at this + time because it is expected the upper 32 bits of these registers will always be zeros. + + For every bit with a defined purpose in an sstateen CSR, the same bit is defined in the + matching mstateen CSR to control access below machine level to the same state. + + Each bit of a stateen CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in sstatus like the + FS and VS fields for the F and V extensions. The number of registers provided at each + level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor + levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to + come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an + attempted compromise between providing too few bits on the one hand and going overboard + with CSRs that will never be used on the other. + + The stateen registers at each level control access to state at all less-privileged levels, + but not at its own level. + + When a stateen CSR prevents access to state for a privilege mode, attempting to execute in + that privilege mode an instruction that implicitly updates the state without reading it may + or may not raise an illegal instruction or virtual instruction exception. Such cases must + be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the ISA + extensions that introduce the controlled state. + Each bit of a supervisor-level sstateen CSR controls user-level access (from U-mode or VU-mode) + to an extension’s state. The intention is to allocate the bits of sstateen CSRs starting at the + least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered + sstateen CSR. + +definedBy: + allOf: + - Smstateen + - Ssstateen + +fields: + DATA: + location: 63-0 + description: Data value + type: RW + reset_value: UNDEFINED_LEGAL diff --git a/arch/ext/Smstateen.yaml b/arch/ext/Smstateen.yaml new file mode 100644 index 000000000..d34259e36 --- /dev/null +++ b/arch/ext/Smstateen.yaml @@ -0,0 +1,25 @@ +# yaml-language-server: $schema=../../schemas/ext_schema.json + +$schema: "ext_schema.json#" +kind: extension +name: Smstateen +long_name: Machine-mode view of the state-enable extension +description: | + Machine-mode view of the state-enable extension. The Smstateen + extension specification comprises the mstateen*, sstateen*, + and hstateen* CSRs and their functionality. + + NOTE: The Smstateen extension specification is an M-mode extension as + it includes M-mode features, but the supervisor-mode visible + components of the extension are named as the Ssstateen extension. Only + Ssstateen is mandated in the RVA22S64 profile when the hypervisor + extension is implemented. These registers are not mandated or + supported options without the hypervisor extension, as there are no + RVA22S64 supported options with relevant state to control in the + absence of the hypervisor extension. + +type: privileged +versions: + - version: "1.0.0" + state: ratified + ratification_date: null From f981030159cfd740c985857c81a2fb6fe703aafe Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 24 Apr 2025 01:23:49 +0000 Subject: [PATCH 02/38] lots of minor fixes --- arch/csr/hstateen0.yaml | 12 +++++++++--- arch/csr/hstateen0h.yaml | 3 ++- arch/csr/hstateen1.yaml | 5 +++-- arch/csr/hstateen1h.yaml | 3 ++- arch/csr/hstateen2.yaml | 5 +++-- arch/csr/hstateen2h.yaml | 3 ++- arch/csr/hstateen3.yaml | 5 +++-- arch/csr/hstateen3h.yaml | 3 ++- arch/csr/mstateen0.yaml | 11 +++++++++-- arch/csr/mstateen0h.yaml | 3 ++- arch/csr/mstateen1.yaml | 5 +++-- arch/csr/mstateen1h.yaml | 3 ++- arch/csr/mstateen2.yaml | 5 +++-- arch/csr/mstateen2h.yaml | 3 ++- arch/csr/mstateen3.yaml | 5 +++-- arch/csr/mstateen3h.yaml | 3 ++- arch/csr/sstateen0.yaml | 2 +- arch/csr/sstateen1.yaml | 5 +++-- arch/csr/sstateen2.yaml | 5 +++-- arch/csr/sstateen3.yaml | 5 +++-- 20 files changed, 62 insertions(+), 32 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index baa4028d5..3d6403941 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -6,7 +6,7 @@ name: hstateen0 long_name: Hypervisor State Enable 0 Register address: 0x60C priv_mode: S -length: 64 +length: MXLEN description: | For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. Bit 63 of hstateen0 controls access to sstateen0. @@ -26,20 +26,23 @@ definedBy: - Smstateen - Ssstateen fields: - SEO: + SE0: location: 63 + base: 64 description: | The SE0 bit in hstateen0 controls access to the sstateen0 CSR. type: RW reset_value: UNDEFINED_LEGAL ENVCFG: location: 62 + base: 64 description: | The ENVCFG bit in hstateen0 controls access to the senvcfg CSRs. type: RW reset_value: UNDEFINED_LEGAL CSRIND: location: 60 + base: 64 description: | The CSRIND bit in hstateen0 controls access to the siselect and the sireg*, (really vsiselect and vsireg*) CSRs provided by the Sscsrind @@ -48,6 +51,7 @@ fields: reset_value: UNDEFINED_LEGAL AIA: location: 59 + base: 64 description: | The AIA bit in hstateen0 controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the @@ -56,6 +60,7 @@ fields: reset_value: UNDEFINED_LEGAL IMSIC: location: 58 + base: 64 description: | The IMSIC bit in hstateen0 controls access to the guest IMSIC state, including CSRs stopei (really vstopei), provided by the Ssaia extension. @@ -66,6 +71,7 @@ fields: reset_value: UNDEFINED_LEGAL CONTEXT: location: 57 + base: 64 description: | The CONTEXT bit in hstateen0 controls access to the scontext CSR provided by the Sdtrig extension. @@ -81,7 +87,7 @@ fields: location: 1 description: | The FCSR bit controls access to fcsr for the case when floating-point instructions - operate on x registers instead of f registers as specified by the Zfinx and related + operate on x registers instead of `f` registers as specified by the Zfinx and related extensions (Zdinx, etc.). Whenever misa.F = 1, FCSR bit of mstateen0 is read-only zero (and hence read-only zero in hstateen0 and sstateen0 too). For convenience, when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a diff --git a/arch/csr/hstateen0h.yaml b/arch/csr/hstateen0h.yaml index 9a7cb17dc..1452c7632 100644 --- a/arch/csr/hstateen0h.yaml +++ b/arch/csr/hstateen0h.yaml @@ -7,6 +7,7 @@ long_name: Upper 32 bits of Hypervisor State Enable 0 Register address: 0x61C priv_mode: S length: 32 +base: 32 description: | For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at @@ -23,7 +24,7 @@ definedBy: - Smstateen - Ssstateen fields: - SEO: + SE0: location: 31 description: | The SE0 bit in hstateen0h controls access to the sstateen0 CSR. diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index f88616275..a5706ab34 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -6,7 +6,7 @@ name: hstateen1 long_name: Hypervisor State Enable 1 Register address: 0x60D priv_mode: S -length: 64 +length: MXLEN description: | For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. Bit 63 of hstateen1 controls access to sstateen1. @@ -26,8 +26,9 @@ definedBy: - Smstateen - Ssstateen fields: - SEO: + SE0: location: 63 + base: 64 description: | The SE0 bit in hstateen1 controls access to the sstateen1 CSR. type: RW diff --git a/arch/csr/hstateen1h.yaml b/arch/csr/hstateen1h.yaml index 207d926cb..41358f4c1 100644 --- a/arch/csr/hstateen1h.yaml +++ b/arch/csr/hstateen1h.yaml @@ -7,6 +7,7 @@ long_name: Upper 32 bits of Hypervisor State Enable 1 Register address: 0x61D priv_mode: S length: 32 +base: 32 description: | For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at @@ -23,7 +24,7 @@ definedBy: - Smstateen - Ssstateen fields: - SEO: + SE0: location: 31 description: | The SE0 bit in hstateen1h controls access to the sstateen1 CSR. diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index af6137b93..27d07c09c 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -6,7 +6,7 @@ name: hstateen2 long_name: Hypervisor State Enable 2 Register address: 0x60E priv_mode: S -length: 64 +length: MXLEN description: | For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. Bit 63 of hstateen2 controls access to sstateen2. @@ -26,8 +26,9 @@ definedBy: - Smstateen - Ssstateen fields: - SEO: + SE0: location: 63 + base: 64 description: | The SE0 bit in hstateen2 controls access to the sstateen2 CSR. type: RW diff --git a/arch/csr/hstateen2h.yaml b/arch/csr/hstateen2h.yaml index b1bd9861b..0afdb78ba 100644 --- a/arch/csr/hstateen2h.yaml +++ b/arch/csr/hstateen2h.yaml @@ -7,6 +7,7 @@ long_name: Upper 32 bits of Hypervisor State Enable 2 Register address: 0x61E priv_mode: S length: 32 +base: 32 description: | For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at @@ -23,7 +24,7 @@ definedBy: - Smstateen - Ssstateen fields: - SEO: + SE0: location: 31 description: | The SE0 bit in hstateen2h controls access to the sstateen2 CSR. diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index 3d7f8bf88..5d477c9d4 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -6,7 +6,7 @@ name: hstateen3 long_name: Hypervisor State Enable 3 Register address: 0x60F priv_mode: S -length: 64 +length: MXLEN description: | For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. Bit 63 of hstateen3 controls access to sstateen3. @@ -26,8 +26,9 @@ definedBy: - Smstateen - Ssstateen fields: - SEO: + SE0: location: 63 + base: 64 description: | The SE0 bit in hstateen3 controls access to the sstateen3 CSR. type: RW diff --git a/arch/csr/hstateen3h.yaml b/arch/csr/hstateen3h.yaml index 738a16ed7..fe6a7fcd0 100644 --- a/arch/csr/hstateen3h.yaml +++ b/arch/csr/hstateen3h.yaml @@ -7,6 +7,7 @@ long_name: Upper 32 bits of Hypervisor State Enable 3 Register address: 0x61F priv_mode: S length: 32 +base: 32 description: | For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at @@ -23,7 +24,7 @@ definedBy: - Smstateen - Ssstateen fields: - SEO: + SE0: location: 31 description: | The SE0 bit in hstateen3h controls access to the sstateen3 CSR. diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index c846428ae..aba545ef7 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -6,7 +6,7 @@ name: mstateen0 long_name: Machine State Enable 0 Register address: 0x30C priv_mode: M -length: 64 +length: MXLEN description: | For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen CSRs. Bit 63 of mstateen0 controls access to sstateen0 and hstateen0. @@ -19,20 +19,23 @@ description: | manage in some other way. definedBy: Smstateen fields: - SEO: + SE0: location: 63 + base: 64 description: | The SE0 bit in mstateen0 controls access to the hstateen0, hstateen0h, and the sstateen0 CSRs. type: RW reset_value: UNDEFINED_LEGAL ENVCFG: location: 62 + base: 64 description: | The ENVCFG bit in mstateen0 controls access to the henvcfg, henvcfgh, and the senvcfg CSRs. type: RW reset_value: UNDEFINED_LEGAL CSRIND: location: 60 + base: 64 description: | The CSRIND bit in mstateen0 controls access to the siselect, sireg*, vsiselect, and the vsireg* CSRs provided by the Sscsrind extensions. @@ -40,6 +43,7 @@ fields: reset_value: UNDEFINED_LEGAL AIA: location: 59 + base: 64 description: | The AIA bit in mstateen0 controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits. @@ -47,6 +51,7 @@ fields: reset_value: UNDEFINED_LEGAL IMSIC: location: 58 + base: 64 description: | The IMSIC bit in mstateen0 controls access to the IMSIC state, including CSRs stopei and vstopei, provided by the Ssaia extension. @@ -54,6 +59,7 @@ fields: reset_value: UNDEFINED_LEGAL CONTEXT: location: 57 + base: 64 description: | The CONTEXT bit in mstateen0 controls access to the scontext and hcontext CSRs provided by the Sdtrig extension. @@ -61,6 +67,7 @@ fields: reset_value: UNDEFINED_LEGAL P1P13: location: 56 + base: 64 description: | The P1P13 bit in mstateen0 controls access to the hedelegh introduced by Privileged Specification Version 1.13. diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml index b6f31f877..d12aace97 100644 --- a/arch/csr/mstateen0h.yaml +++ b/arch/csr/mstateen0h.yaml @@ -7,6 +7,7 @@ long_name: Upper 32 bits of Machine State Enable 0 Register address: 0x31C priv_mode: M length: 32 +base: 32 description: | For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the @@ -14,7 +15,7 @@ description: | mstateen0h, mstateen1h, mstateen2h, mstateen3h. definedBy: Smstateen fields: - SEO: + SE0: location: 31 description: | The SE0 bit in mstateen0h controls access to the hstateen0, hstateen0h, and the sstateen0 CSRs. diff --git a/arch/csr/mstateen1.yaml b/arch/csr/mstateen1.yaml index 778999636..b603ef8a0 100644 --- a/arch/csr/mstateen1.yaml +++ b/arch/csr/mstateen1.yaml @@ -6,7 +6,7 @@ name: mstateen1 long_name: Machine State Enable 1 Register address: 0x30D priv_mode: M -length: 64 +length: MXLEN description: | For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen CSRs. Bit 63 of mstateen1 controls access to sstateen1 and hstateen1. @@ -19,8 +19,9 @@ description: | manage in some other way. definedBy: Smstateen fields: - SEO: + SE0: location: 63 + base: 64 description: | The SE0 bit in mstateen1 controls access to the hstateen1, hstateen1h, and the sstateen1 CSRs. type: RW diff --git a/arch/csr/mstateen1h.yaml b/arch/csr/mstateen1h.yaml index d3720de4e..2f46c5734 100644 --- a/arch/csr/mstateen1h.yaml +++ b/arch/csr/mstateen1h.yaml @@ -7,6 +7,7 @@ long_name: Upper 32 bits of Machine State Enable 1 Register address: 0x31D priv_mode: M length: 32 +base: 32 description: | For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the @@ -14,7 +15,7 @@ description: | mstateen0h, mstateen1h, mstateen2h, mstateen3h. definedBy: Smstateen fields: - SEO: + SE0: location: 31 description: | The SE0 bit in mstateen1h controls access to the hstateen1, hstateen1h, and the sstateen1 CSRs. diff --git a/arch/csr/mstateen2.yaml b/arch/csr/mstateen2.yaml index 7415ed910..c57818c3f 100644 --- a/arch/csr/mstateen2.yaml +++ b/arch/csr/mstateen2.yaml @@ -6,7 +6,7 @@ name: mstateen2 long_name: Machine State Enable 2 Register address: 0x30E priv_mode: M -length: 64 +length: MXLEN description: | For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen CSRs. Bit 63 of mstateen2 controls access to sstateen2 and hstateen2. @@ -19,8 +19,9 @@ description: | manage in some other way. definedBy: Smstateen fields: - SEO: + SE0: location: 63 + base: 64 description: | The SE0 bit in mstateen2 controls access to the hstateen2, hstateen2h, and the sstateen2 CSRs. type: RW diff --git a/arch/csr/mstateen2h.yaml b/arch/csr/mstateen2h.yaml index 3c047c9fe..f85bbd79e 100644 --- a/arch/csr/mstateen2h.yaml +++ b/arch/csr/mstateen2h.yaml @@ -7,6 +7,7 @@ long_name: Upper 32 bits of Machine State Enable 2 Register address: 0x31E priv_mode: M length: 32 +base: 32 description: | For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the @@ -14,7 +15,7 @@ description: | mstateen0h, mstateen1h, mstateen2h, mstateen3h. definedBy: Smstateen fields: - SEO: + SE0: location: 31 description: | The SE0 bit in mstateen2h controls access to the hstateen2, hstateen2h, and the sstateen2 CSRs. diff --git a/arch/csr/mstateen3.yaml b/arch/csr/mstateen3.yaml index e77da9966..09e06b262 100644 --- a/arch/csr/mstateen3.yaml +++ b/arch/csr/mstateen3.yaml @@ -6,7 +6,7 @@ name: mstateen3 long_name: Machine State Enable 3 Register address: 0x30F priv_mode: M -length: 64 +length: MXLEN description: | For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen CSRs. Bit 63 of mstateen3 controls access to sstateen3 and hstateen3. @@ -19,8 +19,9 @@ description: | manage in some other way. definedBy: Smstateen fields: - SEO: + SE0: location: 63 + base: 64 description: | The SE0 bit in mstateen3 controls access to the hstateen3, hstateen3h, and the sstateen3 CSRs. type: RW diff --git a/arch/csr/mstateen3h.yaml b/arch/csr/mstateen3h.yaml index 618be0379..378af10dd 100644 --- a/arch/csr/mstateen3h.yaml +++ b/arch/csr/mstateen3h.yaml @@ -7,6 +7,7 @@ long_name: Upper 32 bits of Machine State Enable 3 Register address: 0x31F priv_mode: M length: 32 +base: 32 description: | For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the @@ -14,7 +15,7 @@ description: | mstateen0h, mstateen1h, mstateen2h, mstateen3h. definedBy: Smstateen fields: - SEO: + SE0: location: 31 description: | The SE0 bit in mstateen3h controls access to the hstateen3, hstateen3h, and the sstateen3 CSRs. diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index 061bad084..e8798b360 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -6,7 +6,7 @@ name: sstateen0 long_name: Supervisor State Enable 0 Register address: 0x10C priv_mode: S -length: 64 +length: MXLEN description: | For the supervisor-level sstateen registers, high-half CSRs are not added at this time because it is expected the upper 32 bits of these registers will always be zeros. diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index 67d98552f..380afb0ab 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -6,7 +6,7 @@ name: sstateen1 long_name: Supervisor State Enable 1 Register address: 0x10D priv_mode: S -length: 64 +length: MXLEN description: | For the supervisor-level sstateen registers, high-half CSRs are not added at this time because it is expected the upper 32 bits of these registers will always be zeros. @@ -44,7 +44,8 @@ definedBy: fields: DATA: - location: 63-0 + location_rv64: 63-0 + location_rv32: 31-0 description: Data value type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index 69e26e930..268b68cf0 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -6,7 +6,7 @@ name: sstateen2 long_name: Supervisor State Enable 2 Register address: 0x10E priv_mode: S -length: 64 +length: MXLEN description: | For the supervisor-level sstateen registers, high-half CSRs are not added at this time because it is expected the upper 32 bits of these registers will always be zeros. @@ -44,7 +44,8 @@ definedBy: fields: DATA: - location: 63-0 + location_rv64: 63-0 + location_rv32: 31-0 description: Data value type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index 02ebe5905..f27b0c280 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -6,7 +6,7 @@ name: sstateen3 long_name: Supervisor State Enable 3 Register address: 0x10F priv_mode: S -length: 64 +length: MXLEN description: | For the supervisor-level sstateen registers, high-half CSRs are not added at this time because it is expected the upper 32 bits of these registers will always be zeros. @@ -44,7 +44,8 @@ definedBy: fields: DATA: - location: 63-0 + location_rv64: 63-0 + location_rv32: 31-0 description: Data value type: RW reset_value: UNDEFINED_LEGAL From 601efbeb33597c59780dea656c9bd2c9ab589d58 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Sat, 26 Apr 2025 00:33:03 +0000 Subject: [PATCH 03/38] lots of backticks --- .pre-commit-config.yaml | 2 +- arch/csr/hstateen0.yaml | 52 ++++++++++++++++++++-------------------- arch/csr/hstateen0h.yaml | 32 ++++++++++++------------- arch/csr/hstateen1.yaml | 16 ++++++------- arch/csr/hstateen1h.yaml | 14 +++++------ arch/csr/hstateen2.yaml | 16 ++++++------- arch/csr/hstateen2h.yaml | 14 +++++------ arch/csr/hstateen3.yaml | 16 ++++++------- arch/csr/hstateen3h.yaml | 14 +++++------ arch/csr/mstateen0.yaml | 44 +++++++++++++++++----------------- arch/csr/mstateen0h.yaml | 20 ++++++++-------- arch/csr/mstateen1.yaml | 12 +++++----- arch/csr/mstateen1h.yaml | 8 +++---- arch/csr/mstateen2.yaml | 12 +++++----- arch/csr/mstateen2h.yaml | 8 +++---- arch/csr/mstateen3.yaml | 12 +++++----- arch/csr/mstateen3h.yaml | 8 +++---- arch/csr/sstateen0.yaml | 42 ++++++++++++++++---------------- arch/csr/sstateen1.yaml | 20 ++++++++-------- arch/csr/sstateen2.yaml | 22 ++++++++--------- arch/csr/sstateen3.yaml | 22 ++++++++--------- 21 files changed, 203 insertions(+), 203 deletions(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 48e68fca8..d247f4708 100755 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -98,4 +98,4 @@ repos: - repo: https://github.com/fsfe/reuse-tool rev: v5.0.2 hooks: - - id: reuse + - id: reuse-lint-file diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 3d6403941..8848bf274 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -8,17 +8,17 @@ address: 0x60C priv_mode: S length: MXLEN description: | - For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. - Bit 63 of hstateen0 controls access to sstateen0. + For each `hstateen` CSR, bit 63 is defined to control access to the matching `sstateen` CSR. + Bit 63 of `hstateen0` controls access to `sstateen0`. - With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling accesses for a virtual machine (from VS and VU modes). - For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), - the same bit appears as read-only zero in sstateen when accessed in VS-mode. + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. - A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one - in the matching mstateen CSR. + A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one + in the matching `mstateen` CSR. definedBy: allOf: @@ -30,22 +30,22 @@ fields: location: 63 base: 64 description: | - The SE0 bit in hstateen0 controls access to the sstateen0 CSR. + The SE0 bit in `hstateen0` controls access to the `sstateen0` CSR. type: RW reset_value: UNDEFINED_LEGAL ENVCFG: location: 62 base: 64 description: | - The ENVCFG bit in hstateen0 controls access to the senvcfg CSRs. + The ENVCFG bit in `hstateen0` controls access to the `senvcfg` CSRs. type: RW reset_value: UNDEFINED_LEGAL CSRIND: location: 60 base: 64 description: | - The CSRIND bit in hstateen0 controls access to the siselect and the - sireg*, (really vsiselect and vsireg*) CSRs provided by the Sscsrind + The CSRIND bit in `hstateen0` controls access to the `siselect` and the + `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind extensions. type: RW reset_value: UNDEFINED_LEGAL @@ -53,19 +53,19 @@ fields: location: 59 base: 64 description: | - The AIA bit in hstateen0 controls access to all state introduced by + The AIA bit in `hstateen0` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the - IMSIC bits of hstateen0. + IMSIC bits of `hstateen0`. type: RW reset_value: UNDEFINED_LEGAL IMSIC: location: 58 base: 64 description: | - The IMSIC bit in hstateen0 controls access to the guest IMSIC state, - including CSRs stopei (really vstopei), provided by the Ssaia extension. + The IMSIC bit in `hstateen0` controls access to the guest IMSIC state, + including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension. - Setting the IMSIC bit in hstateen0 to zero prevents a virtual machine + Setting the IMSIC bit in `hstateen0` to zero prevents a virtual machine from accessing the hart’s IMSIC the same as setting `hstatus.`VGEIN = 0. type: RW reset_value: UNDEFINED_LEGAL @@ -73,27 +73,27 @@ fields: location: 57 base: 64 description: | - The CONTEXT bit in hstateen0 controls access to the scontext CSR provided + The CONTEXT bit in `hstateen0` controls access to the `scontext` CSR provided by the Sdtrig extension. type: RW reset_value: UNDEFINED_LEGAL JVT: location: 2 description: | - The JVT bit controls access to the jvt CSR provided by the Zcmt extension. + The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW reset_value: UNDEFINED_LEGAL FCSR: location: 1 description: | - The FCSR bit controls access to fcsr for the case when floating-point instructions - operate on x registers instead of `f` registers as specified by the Zfinx and related - extensions (Zdinx, etc.). Whenever misa.F = 1, FCSR bit of mstateen0 is read-only - zero (and hence read-only zero in hstateen0 and sstateen0 too). For convenience, - when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a - controlling stateen0 CSR is zero, all floating-point instructions cause an illegal + The FCSR bit controls access to `fcsr` for the case when floating-point instructions + operate on `x` registers instead of `f` registers as specified by the Zfinx and related + extensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit of `mstateen0` is read-only + zero (and hence read-only zero in `hstateen0` and `sstateen0` too). For convenience, + when the `stateen` CSRs are implemented and `misa.F` = 0, then if the FCSR bit of a + controlling `stateen0` CSR is zero, all floating-point instructions cause an illegal instruction trap (or virtual instruction trap, if relevant), as though they all access - fcsr, regardless of whether they really do. + `fcsr`, regardless of whether they really do. type: RW reset_value: UNDEFINED_LEGAL C: @@ -101,6 +101,6 @@ fields: description: | The C bit controls access to any and all custom state. This bit is not custom state itself. The C bit of these registers is not custom state itself; it is a standard field of a - standard CSR, either mstateen0, hstateen0, or sstateen0. + standard CSR, either `mstateen0`, `hstateen0`, or `sstateen0`. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen0h.yaml b/arch/csr/hstateen0h.yaml index 1452c7632..3782ccfc6 100644 --- a/arch/csr/hstateen0h.yaml +++ b/arch/csr/hstateen0h.yaml @@ -9,14 +9,14 @@ priv_mode: S length: 32 base: 32 description: | - For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), - mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at - supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented, - another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3. + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), + `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, + another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding - set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, - hstateen1h, hstateen2h, and hstateen3h. + set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, + `hstateen1h`, `hstateen2h`, and `hstateen3h`. definedBy: allOf: @@ -27,45 +27,45 @@ fields: SE0: location: 31 description: | - The SE0 bit in hstateen0h controls access to the sstateen0 CSR. + The SE0 bit in `hstateen0h` controls access to the `sstateen0` CSR. type: RW reset_value: UNDEFINED_LEGAL ENVCFG: location: 30 description: | - The ENVCFG bit in hstateen0h controls access to the senvcfg CSRs. + The ENVCFG bit in `hstateen0h` controls access to the `senvcfg` CSRs. type: RW reset_value: UNDEFINED_LEGAL CSRIND: location: 28 description: | - The CSRIND bit in hstateen0h controls access to the siselect and the - sireg*, (really vsiselect and vsireg*) CSRs provided by the Sscsrind + The CSRIND bit in `hstateen0h` controls access to the `siselect` and the + `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind extensions. type: RW reset_value: UNDEFINED_LEGAL AIA: location: 27 description: | - The AIA bit in hstateen0h controls access to all state introduced by + The AIA bit in `hstateen0h` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the - IMSIC bits of hstateen0. + IMSIC bits of `hstateen0`. type: RW reset_value: UNDEFINED_LEGAL IMSIC: location: 26 description: | - The IMSIC bit in hstateen0h controls access to the guest IMSIC state, - including CSRs stopei (really vstopei), provided by the Ssaia extension. + The IMSIC bit in `hstateen0h` controls access to the guest IMSIC state, + including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension. - Setting the IMSIC bit in hstateen0h to zero prevents a virtual machine + Setting the IMSIC bit in `hstateen0h` to zero prevents a virtual machine from accessing the hart’s IMSIC the same as setting `hstatus.`VGEIN = 0. type: RW reset_value: UNDEFINED_LEGAL CONTEXT: location: 25 description: | - The CONTEXT bit in hstateen0h controls access to the scontext CSR provided + The CONTEXT bit in `hstateen0h` controls access to the `scontext` CSR provided by the Sdtrig extension. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index a5706ab34..a0a573ada 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -8,17 +8,17 @@ address: 0x60D priv_mode: S length: MXLEN description: | - For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. - Bit 63 of hstateen1 controls access to sstateen1. + For each `hstateen` CSR, bit 63 is defined to control access to the matching `sstateen` CSR. + Bit 63 of `hstateen1` controls access to `sstateen1`. - With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling accesses for a virtual machine (from VS and VU modes). - For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), - the same bit appears as read-only zero in sstateen when accessed in VS-mode. + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. - A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one - in the matching mstateen CSR. + A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one + in the matching `mstateen` CSR. definedBy: allOf: @@ -30,6 +30,6 @@ fields: location: 63 base: 64 description: | - The SE0 bit in hstateen1 controls access to the sstateen1 CSR. + The SE0 bit in `hstateen1` controls access to the `sstateen1` CSR. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen1h.yaml b/arch/csr/hstateen1h.yaml index 41358f4c1..14b4eae18 100644 --- a/arch/csr/hstateen1h.yaml +++ b/arch/csr/hstateen1h.yaml @@ -9,14 +9,14 @@ priv_mode: S length: 32 base: 32 description: | - For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), - mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at - supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented, - another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3. + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), + `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, + another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding - set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, - hstateen1h, hstateen2h, and hstateen3h. + set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, + `hstateen1h`, `hstateen2h`, and `hstateen3h`. definedBy: allOf: @@ -27,6 +27,6 @@ fields: SE0: location: 31 description: | - The SE0 bit in hstateen1h controls access to the sstateen1 CSR. + The SE0 bit in `hstateen1h` controls access to the `sstateen1` CSR. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index 27d07c09c..9d393cd01 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -8,17 +8,17 @@ address: 0x60E priv_mode: S length: MXLEN description: | - For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. - Bit 63 of hstateen2 controls access to sstateen2. + For each `hstateen` CSR, bit 63 is defined to control access to the matching `sstateen` CSR. + Bit 63 of `hstateen2` controls access to `sstateen2`. - With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling accesses for a virtual machine (from VS and VU modes). - For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), - the same bit appears as read-only zero in sstateen when accessed in VS-mode. + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. - A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one - in the matching mstateen CSR. + A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one + in the matching `mstateen` CSR. definedBy: allOf: @@ -30,6 +30,6 @@ fields: location: 63 base: 64 description: | - The SE0 bit in hstateen2 controls access to the sstateen2 CSR. + The SE0 bit in `hstateen2` controls access to the `sstateen2` CSR. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen2h.yaml b/arch/csr/hstateen2h.yaml index 0afdb78ba..13e08613a 100644 --- a/arch/csr/hstateen2h.yaml +++ b/arch/csr/hstateen2h.yaml @@ -9,14 +9,14 @@ priv_mode: S length: 32 base: 32 description: | - For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), - mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at - supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented, - another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3. + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), + `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, + another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding - set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, - hstateen1h, hstateen2h, and hstateen3h. + set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, + `hstateen1h`, `hstateen2h`, and `hstateen3h`. definedBy: allOf: @@ -27,6 +27,6 @@ fields: SE0: location: 31 description: | - The SE0 bit in hstateen2h controls access to the sstateen2 CSR. + The SE0 bit in `hstateen2h` controls access to the `sstateen2` CSR. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index 5d477c9d4..b5c6a3e3a 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -8,17 +8,17 @@ address: 0x60F priv_mode: S length: MXLEN description: | - For each hstateen CSR, bit 63 is defined to control access to the matching sstateen CSR. - Bit 63 of hstateen3 controls access to sstateen3. + For each `hstateen` CSR, bit 63 is defined to control access to the matching `sstateen` CSR. + Bit 63 of `hstateen3` controls access to `sstateen3`. - With the hypervisor extension, the hstateen CSRs have identical encodings to the mstateen + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling accesses for a virtual machine (from VS and VU modes). - For every bit in an hstateen CSR that is zero (whether read-only zero or set to zero), - the same bit appears as read-only zero in sstateen when accessed in VS-mode. + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. - A bit in an hstateen CSR cannot be read-only one unless the same bit is read-only one - in the matching mstateen CSR. + A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one + in the matching `mstateen` CSR. definedBy: allOf: @@ -30,6 +30,6 @@ fields: location: 63 base: 64 description: | - The SE0 bit in hstateen3 controls access to the sstateen3 CSR. + The SE0 bit in `hstateen3` controls access to the `sstateen3` CSR. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/hstateen3h.yaml b/arch/csr/hstateen3h.yaml index fe6a7fcd0..6785303a8 100644 --- a/arch/csr/hstateen3h.yaml +++ b/arch/csr/hstateen3h.yaml @@ -9,14 +9,14 @@ priv_mode: S length: 32 base: 32 description: | - For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State Enable 0), - mstateen1, mstateen2, and mstateen3. If supervisor mode is implemented, another four CSRs are defined at - supervisor level: sstateen0, sstateen1, sstateen2, and sstateen3. And if the hypervisor extension is implemented, - another set of CSRs is added: hstateen0, hstateen1, hstateen2, and hstateen3. + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), + `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, + another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding - set of high-half CSRs for the upper 32 bits of each register: mstateen0h, mstateen1h, mstateen2h, mstateen3h, hstateen0h, - hstateen1h, hstateen2h, and hstateen3h. + set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, + `hstateen1h`, `hstateen2h`, and `hstateen3h`. definedBy: allOf: @@ -27,6 +27,6 @@ fields: SE0: location: 31 description: | - The SE0 bit in hstateen3h controls access to the sstateen3 CSR. + The SE0 bit in `hstateen3h` controls access to the `sstateen3` CSR. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index aba545ef7..5457f9e31 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -8,12 +8,12 @@ address: 0x30C priv_mode: M length: MXLEN description: | - For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen - CSRs. Bit 63 of mstateen0 controls access to sstateen0 and hstateen0. + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` + CSRs. Bit 63 of `mstateen0` controls access to `sstateen0` and `hstateen0`. - On reset, all writable mstateen bits are initialized by the hardware to zeros. If machine-level software - changes these values, it is responsible for initializing the corresponding writable bits of the hstateen - and sstateen CSRs to zeros too. Software at each privilege level should set its respective stateen CSRs + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software + changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` + and `sstateen` CSRs to zeros too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to manage in some other way. @@ -23,21 +23,21 @@ fields: location: 63 base: 64 description: | - The SE0 bit in mstateen0 controls access to the hstateen0, hstateen0h, and the sstateen0 CSRs. + The SE0 bit in `mstateen0` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs. type: RW reset_value: UNDEFINED_LEGAL ENVCFG: location: 62 base: 64 description: | - The ENVCFG bit in mstateen0 controls access to the henvcfg, henvcfgh, and the senvcfg CSRs. + The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs. type: RW reset_value: UNDEFINED_LEGAL CSRIND: location: 60 base: 64 description: | - The CSRIND bit in mstateen0 controls access to the siselect, sireg*, vsiselect, and the vsireg* + The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions. type: RW reset_value: UNDEFINED_LEGAL @@ -45,7 +45,7 @@ fields: location: 59 base: 64 description: | - The AIA bit in mstateen0 controls access to all state introduced by the Ssaia extension and is not + The AIA bit in `mstateen0` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits. type: RW reset_value: UNDEFINED_LEGAL @@ -53,7 +53,7 @@ fields: location: 58 base: 64 description: | - The IMSIC bit in mstateen0 controls access to the IMSIC state, including CSRs stopei and vstopei, + The IMSIC bit in `mstateen0` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, provided by the Ssaia extension. type: RW reset_value: UNDEFINED_LEGAL @@ -61,7 +61,7 @@ fields: location: 57 base: 64 description: | - The CONTEXT bit in mstateen0 controls access to the scontext and hcontext CSRs provided by the + The CONTEXT bit in `mstateen0` controls access to the `scontext` and `hcontext` CSRs provided by the Sdtrig extension. type: RW reset_value: UNDEFINED_LEGAL @@ -69,34 +69,34 @@ fields: location: 56 base: 64 description: | - The P1P13 bit in mstateen0 controls access to the hedelegh introduced by Privileged Specification + The P1P13 bit in `mstateen0` controls access to the `hedelegh` introduced by Privileged Specification Version 1.13. type: RW reset_value: UNDEFINED_LEGAL JVT: location: 2 description: | - The JVT bit controls access to the jvt CSR provided by the Zcmt extension. + The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW reset_value: UNDEFINED_LEGAL FCSR: location: 1 description: | - The FCSR bit controls access to fcsr for the case when floating-point instructions - operate on x registers instead of f registers as specified by the Zfinx and related - extensions (Zdinx, etc.). Whenever misa.F = 1, FCSR bit of mstateen0 is read-only - zero (and hence read-only zero in hstateen0 and sstateen0 too). For convenience, - when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a - controlling stateen0 CSR is zero, all floating-point instructions cause an illegal + The FCSR bit controls access to `fcsr` for the case when floating-point instructions + operate on `x` registers instead of `f` registers as specified by the Zfinx and related + extensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit of `mstateen0` is read-only + zero (and hence read-only zero in `hstateen0` and `sstateen0` too). For convenience, + when the `stateen` CSRs are implemented and `misa.F` = 0, then if the FCSR bit of a + controlling `stateen0` CSR is zero, all floating-point instructions cause an illegal instruction trap (or virtual instruction trap, if relevant), as though they all access - fcsr, regardless of whether they really do. + `fcsr`, regardless of whether they really do. type: RW reset_value: UNDEFINED_LEGAL C: location: 0 description: | The C bit controls access to any and all custom state. This bit is not custom state itself. The C bit of - these registers is not custom state itself; it is a standard field of a standard CSR, either mstateen0, - hstateen0, or sstateen0. + these registers is not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, + `hstateen0`, or `sstateen0`. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml index d12aace97..9d00b3cb8 100644 --- a/arch/csr/mstateen0h.yaml +++ b/arch/csr/mstateen0h.yaml @@ -9,56 +9,56 @@ priv_mode: M length: 32 base: 32 description: | - For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State - Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State + Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: - mstateen0h, mstateen1h, mstateen2h, mstateen3h. + `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. definedBy: Smstateen fields: SE0: location: 31 description: | - The SE0 bit in mstateen0h controls access to the hstateen0, hstateen0h, and the sstateen0 CSRs. + The SE0 bit in `mstateen0h` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs. type: RW reset_value: UNDEFINED_LEGAL ENVCFG: location: 30 description: | - The ENVCFG bit in mstateen0h controls access to the henvcfg, henvcfgh, and the senvcfg CSRs. + The ENVCFG bit in `mstateen0h` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs. type: RW reset_value: UNDEFINED_LEGAL CSRIND: location: 28 description: | - The CSRIND bit in mstateen0h controls access to the siselect, sireg*, vsiselect, and the vsireg* + The CSRIND bit in `mstateen0h` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions. type: RW reset_value: UNDEFINED_LEGAL AIA: location: 27 description: | - The AIA bit in mstateen0h controls access to all state introduced by the Ssaia extension and is not + The AIA bit in `mstateen0h` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits. type: RW reset_value: UNDEFINED_LEGAL IMSIC: location: 26 description: | - The IMSIC bit in mstateen0h controls access to the IMSIC state, including CSRs stopei and vstopei, + The IMSIC bit in `mstateen0h` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, provided by the Ssaia extension. type: RW reset_value: UNDEFINED_LEGAL CONTEXT: location: 25 description: | - The CONTEXT bit in mstateen0h controls access to the scontext and hcontext CSRs provided by the + The CONTEXT bit in `mstateen0h` controls access to the `scontext` and `hcontext` CSRs provided by the Sdtrig extension. type: RW reset_value: UNDEFINED_LEGAL P1P13: location: 24 description: | - The P1P13 bit in mstateen0h controls access to the hedelegh introduced by Privileged Specification + The P1P13 bit in `mstateen0h` controls access to the `hedelegh` introduced by Privileged Specification Version 1.13. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen1.yaml b/arch/csr/mstateen1.yaml index b603ef8a0..9e65135b6 100644 --- a/arch/csr/mstateen1.yaml +++ b/arch/csr/mstateen1.yaml @@ -8,12 +8,12 @@ address: 0x30D priv_mode: M length: MXLEN description: | - For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen - CSRs. Bit 63 of mstateen1 controls access to sstateen1 and hstateen1. + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` + CSRs. Bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`. - On reset, all writable mstateen bits are initialized by the hardware to zeros. If machine-level software - changes these values, it is responsible for initializing the corresponding writable bits of the hstateen - and sstateen CSRs to zeros too. Software at each privilege level should set its respective stateen CSRs + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software + changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` + and `sstateen` CSRs to zeros too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to manage in some other way. @@ -23,6 +23,6 @@ fields: location: 63 base: 64 description: | - The SE0 bit in mstateen1 controls access to the hstateen1, hstateen1h, and the sstateen1 CSRs. + The SE0 bit in `mstateen1` controls access to the `hstateen1`, `hstateen1h`, and the `sstateen1` CSRs. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen1h.yaml b/arch/csr/mstateen1h.yaml index 2f46c5734..f478323b9 100644 --- a/arch/csr/mstateen1h.yaml +++ b/arch/csr/mstateen1h.yaml @@ -9,15 +9,15 @@ priv_mode: M length: 32 base: 32 description: | - For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State - Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State + Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: - mstateen0h, mstateen1h, mstateen2h, mstateen3h. + `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. definedBy: Smstateen fields: SE0: location: 31 description: | - The SE0 bit in mstateen1h controls access to the hstateen1, hstateen1h, and the sstateen1 CSRs. + The SE0 bit in `mstateen1h` controls access to the `hstateen1`, `hstateen1h`, and the `sstateen1` CSRs. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen2.yaml b/arch/csr/mstateen2.yaml index c57818c3f..9326cf7c2 100644 --- a/arch/csr/mstateen2.yaml +++ b/arch/csr/mstateen2.yaml @@ -8,12 +8,12 @@ address: 0x30E priv_mode: M length: MXLEN description: | - For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen - CSRs. Bit 63 of mstateen2 controls access to sstateen2 and hstateen2. + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` + CSRs. Bit 63 of `mstateen2` controls access to `sstateen2` and `hstateen2`. - On reset, all writable mstateen bits are initialized by the hardware to zeros. If machine-level software - changes these values, it is responsible for initializing the corresponding writable bits of the hstateen - and sstateen CSRs to zeros too. Software at each privilege level should set its respective stateen CSRs + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software + changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` + and `sstateen` CSRs to zeros too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to manage in some other way. @@ -23,6 +23,6 @@ fields: location: 63 base: 64 description: | - The SE0 bit in mstateen2 controls access to the hstateen2, hstateen2h, and the sstateen2 CSRs. + The SE0 bit in `mstateen2` controls access to the `hstateen2`, `hstateen2h`, and the `sstateen2` CSRs. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen2h.yaml b/arch/csr/mstateen2h.yaml index f85bbd79e..ccad4f6e3 100644 --- a/arch/csr/mstateen2h.yaml +++ b/arch/csr/mstateen2h.yaml @@ -9,15 +9,15 @@ priv_mode: M length: 32 base: 32 description: | - For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State - Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State + Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: - mstateen0h, mstateen1h, mstateen2h, mstateen3h. + `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. definedBy: Smstateen fields: SE0: location: 31 description: | - The SE0 bit in mstateen2h controls access to the hstateen2, hstateen2h, and the sstateen2 CSRs. + The SE0 bit in `mstateen2h` controls access to the `hstateen2`, `hstateen2h`, and the `sstateen2` CSRs. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen3.yaml b/arch/csr/mstateen3.yaml index 09e06b262..963e78865 100644 --- a/arch/csr/mstateen3.yaml +++ b/arch/csr/mstateen3.yaml @@ -8,12 +8,12 @@ address: 0x30F priv_mode: M length: MXLEN description: | - For each mstateen CSR, bit 63 is defined to control access to the matching sstateen and hstateen - CSRs. Bit 63 of mstateen3 controls access to sstateen3 and hstateen3. + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` + CSRs. Bit 63 of `mstateen3` controls access to `sstateen3` and `hstateen3`. - On reset, all writable mstateen bits are initialized by the hardware to zeros. If machine-level software - changes these values, it is responsible for initializing the corresponding writable bits of the hstateen - and sstateen CSRs to zeros too. Software at each privilege level should set its respective stateen CSRs + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software + changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` + and `sstateen` CSRs to zeros too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to manage in some other way. @@ -23,6 +23,6 @@ fields: location: 63 base: 64 description: | - The SE0 bit in mstateen3 controls access to the hstateen3, hstateen3h, and the sstateen3 CSRs. + The SE0 bit in `mstateen3` controls access to the `hstateen3`, `hstateen3h`, and the `sstateen3` CSRs. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/mstateen3h.yaml b/arch/csr/mstateen3h.yaml index 378af10dd..0a9fed075 100644 --- a/arch/csr/mstateen3h.yaml +++ b/arch/csr/mstateen3h.yaml @@ -9,15 +9,15 @@ priv_mode: M length: 32 base: 32 description: | - For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: mstateen0 (Machine State - Enable 0), mstateen1, mstateen2, and mstateen3. For RV32, the registers listed above are 32-bit, and for the + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State + Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: - mstateen0h, mstateen1h, mstateen2h, mstateen3h. + `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. definedBy: Smstateen fields: SE0: location: 31 description: | - The SE0 bit in mstateen3h controls access to the hstateen3, hstateen3h, and the sstateen3 CSRs. + The SE0 bit in `mstateen3h` controls access to the `hstateen3`, `hstateen3h`, and the `sstateen3` CSRs. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index e8798b360..b8e414243 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -8,14 +8,14 @@ address: 0x10C priv_mode: S length: MXLEN description: | - For the supervisor-level sstateen registers, high-half CSRs are not added at this + For the supervisor-level `sstateen` registers, high-half CSRs are not added at this time because it is expected the upper 32 bits of these registers will always be zeros. - For every bit with a defined purpose in an sstateen CSR, the same bit is defined in the - matching mstateen CSR to control access below machine level to the same state. + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the + matching `mstateen` CSR to control access below machine level to the same state. - Each bit of a stateen CSR controls less-privileged access to an extension’s state, - for an extension that was not deemed "worthy" of a full XS field in sstatus like the + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. The number of registers provided at each level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to @@ -23,19 +23,19 @@ description: | attempted compromise between providing too few bits on the one hand and going overboard with CSRs that will never be used on the other. - The stateen registers at each level control access to state at all less-privileged levels, + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - When a stateen CSR prevents access to state for a privilege mode, attempting to execute in + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the ISA + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state. - Each bit of a supervisor-level sstateen CSR controls user-level access (from U-mode or VU-mode) - to an extension’s state. The intention is to allocate the bits of sstateen CSRs starting at the + Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) + to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered - sstateen CSR. + `sstateen` CSR. definedBy: allOf: @@ -45,27 +45,27 @@ fields: JVT: location: 2 description: | - The JVT bit controls access to the jvt CSR provided by the Zcmt extension. + The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW reset_value: UNDEFINED_LEGAL FCSR: location: 1 description: | - The FCSR bit controls access to fcsr for the case when floating-point instructions - operate on x registers instead of f registers as specified by the Zfinx and related - extensions (Zdinx, etc.). Whenever misa.F = 1, FCSR bit of mstateen0 is read-only - zero (and hence read-only zero in hstateen0 and sstateen0 too). For convenience, - when the stateen CSRs are implemented and misa.F = 0, then if the FCSR bit of a - controlling stateen0 CSR is zero, all floating-point instructions cause an illegal + The FCSR bit controls access to `fcsr` for the case when floating-point instructions + operate on `x` registers instead of `f` registers as specified by the Zfinx and related + extensions (Zdinx, etc.). Whenever `misa.F` = 1, FCSR bit of `mstateen0` is read-only + zero (and hence read-only zero in `hstateen0` and `sstateen0` too). For convenience, + when the `stateen` CSRs are implemented and `misa.F` = 0, then if the FCSR bit of a + controlling `stateen0` CSR is zero, all floating-point instructions cause an illegal instruction trap (or virtual instruction trap, if relevant), as though they all access - fcsr, regardless of whether they really do. + `fcsr`, regardless of whether they really do. type: RW reset_value: UNDEFINED_LEGAL C: location: 0 description: | The C bit controls access to any and all custom state. This bit is not custom state itself. The C bit of - these registers is not custom state itself; it is a standard field of a standard CSR, either mstateen0, - hstateen0, or sstateen0. + these registers is not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, + `hstateen0`, or `sstateen0`. type: RW reset_value: UNDEFINED_LEGAL diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index 380afb0ab..7a521dfee 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -8,14 +8,14 @@ address: 0x10D priv_mode: S length: MXLEN description: | - For the supervisor-level sstateen registers, high-half CSRs are not added at this + For the supervisor-level `sstateen` registers, high-half CSRs are not added at this time because it is expected the upper 32 bits of these registers will always be zeros. - For every bit with a defined purpose in an sstateen CSR, the same bit is defined in the - matching mstateen CSR to control access below machine level to the same state. + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the + matching `mstateen` CSR to control access below machine level to the same state. - Each bit of a stateen CSR controls less-privileged access to an extension’s state, - for an extension that was not deemed "worthy" of a full XS field in sstatus like the + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. The number of registers provided at each level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to @@ -23,17 +23,17 @@ description: | attempted compromise between providing too few bits on the one hand and going overboard with CSRs that will never be used on the other. - The stateen registers at each level control access to state at all less-privileged levels, + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - When a stateen CSR prevents access to state for a privilege mode, attempting to execute in + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the ISA + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state. - Each bit of a supervisor-level sstateen CSR controls user-level access (from U-mode or VU-mode) - to an extension’s state. The intention is to allocate the bits of sstateen CSRs starting at the + Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) + to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered sstateen CSR. diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index 268b68cf0..12895f559 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -8,14 +8,14 @@ address: 0x10E priv_mode: S length: MXLEN description: | - For the supervisor-level sstateen registers, high-half CSRs are not added at this + For the supervisor-level `sstateen` registers, high-half CSRs are not added at this time because it is expected the upper 32 bits of these registers will always be zeros. - For every bit with a defined purpose in an sstateen CSR, the same bit is defined in the - matching mstateen CSR to control access below machine level to the same state. + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the + matching `mstateen` CSR to control access below machine level to the same state. - Each bit of a stateen CSR controls less-privileged access to an extension’s state, - for an extension that was not deemed "worthy" of a full XS field in sstatus like the + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. The number of registers provided at each level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to @@ -23,19 +23,19 @@ description: | attempted compromise between providing too few bits on the one hand and going overboard with CSRs that will never be used on the other. - The stateen registers at each level control access to state at all less-privileged levels, + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - When a stateen CSR prevents access to state for a privilege mode, attempting to execute in + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the ISA + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state. - Each bit of a supervisor-level sstateen CSR controls user-level access (from U-mode or VU-mode) - to an extension’s state. The intention is to allocate the bits of sstateen CSRs starting at the + Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) + to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered - sstateen CSR. + `sstateen` CSR. definedBy: allOf: diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index f27b0c280..e6410a573 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -8,14 +8,14 @@ address: 0x10F priv_mode: S length: MXLEN description: | - For the supervisor-level sstateen registers, high-half CSRs are not added at this + For the supervisor-level `sstateen` registers, high-half CSRs are not added at this time because it is expected the upper 32 bits of these registers will always be zeros. - For every bit with a defined purpose in an sstateen CSR, the same bit is defined in the - matching mstateen CSR to control access below machine level to the same state. + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the + matching `mstateen` CSR to control access below machine level to the same state. - Each bit of a stateen CSR controls less-privileged access to an extension’s state, - for an extension that was not deemed "worthy" of a full XS field in sstatus like the + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. The number of registers provided at each level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to @@ -23,19 +23,19 @@ description: | attempted compromise between providing too few bits on the one hand and going overboard with CSRs that will never be used on the other. - The stateen registers at each level control access to state at all less-privileged levels, + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - When a stateen CSR prevents access to state for a privilege mode, attempting to execute in + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - In some cases, the bits of the stateen CSRs will have a dual purpose as enables for the ISA + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state. - Each bit of a supervisor-level sstateen CSR controls user-level access (from U-mode or VU-mode) - to an extension’s state. The intention is to allocate the bits of sstateen CSRs starting at the + Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) + to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered - sstateen CSR. + `sstateen` CSR. definedBy: allOf: From a5108d2e6cc36c83458083c3ddaf6630fc72c991 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Mon, 28 Apr 2025 20:27:48 +0000 Subject: [PATCH 04/38] minor fixes --- arch/csr/hstateen0.yaml | 19 +++++++++++++++++++ arch/csr/sstateen0.yaml | 3 ++- arch/csr/sstateen1.yaml | 3 ++- arch/csr/sstateen2.yaml | 3 ++- arch/csr/sstateen3.yaml | 3 ++- arch/ext/Smstateen.yaml | 4 ++-- 6 files changed, 29 insertions(+), 6 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 8848bf274..8ab0de3d2 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -8,6 +8,25 @@ address: 0x60C priv_mode: S length: MXLEN description: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. The number of registers provided at each + level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor + levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to + come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an + attempted compromise between providing too few bits on the one hand and going overboard + with CSRs that will never be used on the other. + + The `stateen` registers at each level control access to state at all less-privileged levels, + but not at its own level. + + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in + that privilege mode an instruction that implicitly updates the state without reading it may + or may not raise an illegal instruction or virtual instruction exception. Such cases must + be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA + extensions that introduce the controlled state. + For each `hstateen` CSR, bit 63 is defined to control access to the matching `sstateen` CSR. Bit 63 of `hstateen0` controls access to `sstateen0`. diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index b8e414243..a3652cbff 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -32,9 +32,10 @@ description: | be disambiguated by being explicitly specified one way or the other. In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state. + Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the - least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered + least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered `sstateen` CSR. definedBy: diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index 7a521dfee..bed248537 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -32,9 +32,10 @@ description: | be disambiguated by being explicitly specified one way or the other. In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state. + Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the - least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered + least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered sstateen CSR. definedBy: diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index 12895f559..763bad8b0 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -32,9 +32,10 @@ description: | be disambiguated by being explicitly specified one way or the other. In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state. + Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the - least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered + least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered `sstateen` CSR. definedBy: diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index e6410a573..27dcf98d3 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -32,9 +32,10 @@ description: | be disambiguated by being explicitly specified one way or the other. In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that introduce the controlled state. + Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the - least- significant end, bit 0, through to bit 31, and then on to the next-higher-numbered + least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered `sstateen` CSR. definedBy: diff --git a/arch/ext/Smstateen.yaml b/arch/ext/Smstateen.yaml index d34259e36..5b38200ca 100644 --- a/arch/ext/Smstateen.yaml +++ b/arch/ext/Smstateen.yaml @@ -6,8 +6,8 @@ name: Smstateen long_name: Machine-mode view of the state-enable extension description: | Machine-mode view of the state-enable extension. The Smstateen - extension specification comprises the mstateen*, sstateen*, - and hstateen* CSRs and their functionality. + extension specification comprises the `mstateen*`, `sstateen*`, + and `hstateen*` CSRs and their functionality. NOTE: The Smstateen extension specification is an M-mode extension as it includes M-mode features, but the supervisor-mode visible From 8bb0d3001b2311f3164c443d1d7a55e9b8c8c218 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Tue, 29 Apr 2025 15:47:34 +0000 Subject: [PATCH 05/38] modified descriptions --- arch/csr/hstateen0.yaml | 67 +++++++++++++++++++----------- arch/csr/hstateen1.yaml | 54 ++++++++++++++++++++---- arch/csr/hstateen2.yaml | 54 ++++++++++++++++++++---- arch/csr/hstateen3.yaml | 54 ++++++++++++++++++++---- arch/csr/mstateen0.yaml | 64 +++++++++++++++++++++++++---- arch/csr/mstateen1.yaml | 66 ++++++++++++++++++++++++++---- arch/csr/mstateen2.yaml | 66 ++++++++++++++++++++++++++---- arch/csr/mstateen3.yaml | 66 ++++++++++++++++++++++++++---- arch/csr/sstateen0.yaml | 81 +++++++++++++++++++++++++----------- arch/csr/sstateen1.yaml | 91 ++++++++++++++++++++++++++++------------- arch/csr/sstateen2.yaml | 91 ++++++++++++++++++++++++++++------------- arch/csr/sstateen3.yaml | 91 ++++++++++++++++++++++++++++------------- 12 files changed, 651 insertions(+), 194 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 8ab0de3d2..0d8a8c1b4 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -8,36 +8,55 @@ address: 0x60C priv_mode: S length: MXLEN description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, - for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the - FS and VS fields for the F and V extensions. The number of registers provided at each - level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor - levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to - come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an - attempted compromise between providing too few bits on the one hand and going overboard - with CSRs that will never be used on the other. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - The `stateen` registers at each level control access to state at all less-privileged levels, - but not at its own level. + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in - that privilege mode an instruction that implicitly updates the state without reading it may - or may not raise an illegal instruction or virtual instruction exception. Such cases must - be disambiguated by being explicitly specified one way or the other. - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA - extensions that introduce the controlled state. + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - For each `hstateen` CSR, bit 63 is defined to control access to the matching `sstateen` CSR. - Bit 63 of `hstateen0` controls access to `sstateen0`. + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` - CSRs, except controlling accesses for a virtual machine (from VS and VU modes). + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. - For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), - the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling + accesses for a virtual machine (from VS and VU modes). - A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one - in the matching `mstateen` CSR. + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine + an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. + + Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over + accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. definedBy: allOf: diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index a0a573ada..ac80243ae 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -8,17 +8,55 @@ address: 0x60D priv_mode: S length: MXLEN description: | - For each `hstateen` CSR, bit 63 is defined to control access to the matching `sstateen` CSR. - Bit 63 of `hstateen1` controls access to `sstateen1`. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` - CSRs, except controlling accesses for a virtual machine (from VS and VU modes). + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. - For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), - the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one - in the matching `mstateen` CSR. + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. + + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. + + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling + accesses for a virtual machine (from VS and VU modes). + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine + an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. + + Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over + accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. definedBy: allOf: diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index 9d393cd01..b26edfe1a 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -8,17 +8,55 @@ address: 0x60E priv_mode: S length: MXLEN description: | - For each `hstateen` CSR, bit 63 is defined to control access to the matching `sstateen` CSR. - Bit 63 of `hstateen2` controls access to `sstateen2`. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` - CSRs, except controlling accesses for a virtual machine (from VS and VU modes). + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. - For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), - the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one - in the matching `mstateen` CSR. + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. + + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. + + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling + accesses for a virtual machine (from VS and VU modes). + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine + an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. + + Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over + accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. definedBy: allOf: diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index b5c6a3e3a..99e682fae 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -8,17 +8,55 @@ address: 0x60F priv_mode: S length: MXLEN description: | - For each `hstateen` CSR, bit 63 is defined to control access to the matching `sstateen` CSR. - Bit 63 of `hstateen3` controls access to `sstateen3`. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` - CSRs, except controlling accesses for a virtual machine (from VS and VU modes). + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. - For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), - the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one - in the matching `mstateen` CSR. + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. + + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. + + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling + accesses for a virtual machine (from VS and VU modes). + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine + an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. + + Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over + accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. definedBy: allOf: diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index 5457f9e31..2bcf4a860 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -8,15 +8,63 @@ address: 0x30C priv_mode: M length: MXLEN description: | - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` - CSRs. Bit 63 of `mstateen0` controls access to `sstateen0` and `hstateen0`. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. + + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. + + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. + + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. + + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. + + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching + supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access + the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always + writable (not read-only). - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software - changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` - and `sstateen` CSRs to zeros too. Software at each privilege level should set its respective `stateen` CSRs - to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, - this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to - manage in some other way. definedBy: Smstateen fields: SE0: diff --git a/arch/csr/mstateen1.yaml b/arch/csr/mstateen1.yaml index 9e65135b6..55b7d4ed0 100644 --- a/arch/csr/mstateen1.yaml +++ b/arch/csr/mstateen1.yaml @@ -8,15 +8,63 @@ address: 0x30D priv_mode: M length: MXLEN description: | - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` - CSRs. Bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software - changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` - and `sstateen` CSRs to zeros too. Software at each privilege level should set its respective `stateen` CSRs - to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, - this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to - manage in some other way. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. + + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. + + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. + + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. + + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. + + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching + supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access + the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always + writable (not read-only). + definedBy: Smstateen fields: SE0: diff --git a/arch/csr/mstateen2.yaml b/arch/csr/mstateen2.yaml index 9326cf7c2..b82c1c440 100644 --- a/arch/csr/mstateen2.yaml +++ b/arch/csr/mstateen2.yaml @@ -8,15 +8,63 @@ address: 0x30E priv_mode: M length: MXLEN description: | - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` - CSRs. Bit 63 of `mstateen2` controls access to `sstateen2` and `hstateen2`. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software - changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` - and `sstateen` CSRs to zeros too. Software at each privilege level should set its respective `stateen` CSRs - to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, - this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to - manage in some other way. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. + + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. + + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. + + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. + + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. + + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching + supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access + the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always + writable (not read-only). + definedBy: Smstateen fields: SE0: diff --git a/arch/csr/mstateen3.yaml b/arch/csr/mstateen3.yaml index 963e78865..50405cce0 100644 --- a/arch/csr/mstateen3.yaml +++ b/arch/csr/mstateen3.yaml @@ -8,15 +8,63 @@ address: 0x30F priv_mode: M length: MXLEN description: | - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` - CSRs. Bit 63 of `mstateen3` controls access to `sstateen3` and `hstateen3`. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software - changes these values, it is responsible for initializing the corresponding writable bits of the `hstateen` - and `sstateen` CSRs to zeros too. Software at each privilege level should set its respective `stateen` CSRs - to indicate the state it is prepared to allow less-privileged software to access. For OSes and hypervisors, - this usually means the state that the OS or hypervisor is prepared to swap on a context switch, or to - manage in some other way. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. + + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. + + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. + + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. + + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. + + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching + supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access + the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always + writable (not read-only). + definedBy: Smstateen fields: SE0: diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index a3652cbff..ba5d67f9d 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -8,35 +8,68 @@ address: 0x10C priv_mode: S length: MXLEN description: | - For the supervisor-level `sstateen` registers, high-half CSRs are not added at this - time because it is expected the upper 32 bits of these registers will always be zeros. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the - matching `mstateen` CSR to control access below machine level to the same state. + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, - for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the - FS and VS fields for the F and V extensions. The number of registers provided at each - level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor - levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to - come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an - attempted compromise between providing too few bits on the one hand and going overboard - with CSRs that will never be used on the other. + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - The `stateen` registers at each level control access to state at all less-privileged levels, - but not at its own level. + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in - that privilege mode an instruction that implicitly updates the state without reading it may - or may not raise an illegal instruction or virtual instruction exception. Such cases must - be disambiguated by being explicitly specified one way or the other. - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA - extensions that introduce the controlled state. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. - Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) - to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the - least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered - `sstateen` CSR. + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine + an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. + + Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over + accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. + + Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching + supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access + the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always + writable (not read-only). definedBy: allOf: diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index bed248537..5afd4e46f 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -8,35 +8,68 @@ address: 0x10D priv_mode: S length: MXLEN description: | - For the supervisor-level `sstateen` registers, high-half CSRs are not added at this - time because it is expected the upper 32 bits of these registers will always be zeros. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the - matching `mstateen` CSR to control access below machine level to the same state. - - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, - for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the - FS and VS fields for the F and V extensions. The number of registers provided at each - level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor - levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to - come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an - attempted compromise between providing too few bits on the one hand and going overboard - with CSRs that will never be used on the other. - - The `stateen` registers at each level control access to state at all less-privileged levels, - but not at its own level. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in - that privilege mode an instruction that implicitly updates the state without reading it may - or may not raise an illegal instruction or virtual instruction exception. Such cases must - be disambiguated by being explicitly specified one way or the other. - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA - extensions that introduce the controlled state. - - Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) - to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the - least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered - sstateen CSR. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. + + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. + + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. + + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. + + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. + + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine + an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. + + Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over + accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. + + Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching + supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access + the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always + writable (not read-only). definedBy: allOf: diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index 763bad8b0..e753d8dff 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -8,35 +8,68 @@ address: 0x10E priv_mode: S length: MXLEN description: | - For the supervisor-level `sstateen` registers, high-half CSRs are not added at this - time because it is expected the upper 32 bits of these registers will always be zeros. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the - matching `mstateen` CSR to control access below machine level to the same state. - - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, - for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the - FS and VS fields for the F and V extensions. The number of registers provided at each - level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor - levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to - come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an - attempted compromise between providing too few bits on the one hand and going overboard - with CSRs that will never be used on the other. - - The `stateen` registers at each level control access to state at all less-privileged levels, - but not at its own level. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in - that privilege mode an instruction that implicitly updates the state without reading it may - or may not raise an illegal instruction or virtual instruction exception. Such cases must - be disambiguated by being explicitly specified one way or the other. - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA - extensions that introduce the controlled state. - - Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) - to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the - least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered - `sstateen` CSR. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. + + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. + + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. + + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. + + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. + + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine + an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. + + Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over + accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. + + Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching + supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access + the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always + writable (not read-only). definedBy: allOf: diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index 27dcf98d3..a767874da 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -8,35 +8,68 @@ address: 0x10F priv_mode: S length: MXLEN description: | - For the supervisor-level `sstateen` registers, high-half CSRs are not added at this - time because it is expected the upper 32 bits of these registers will always be zeros. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the - matching `mstateen` CSR to control access below machine level to the same state. - - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, - for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the - FS and VS fields for the F and V extensions. The number of registers provided at each - level is four because it is believed that 4 * 64 = 256 bits for machine and hypervisor - levels, and 4 * 32 = 128 bits for supervisor level, will be adequate for many years to - come, perhaps for as long as the RISC-V ISA is in use. The exact number four is an - attempted compromise between providing too few bits on the one hand and going overboard - with CSRs that will never be used on the other. - - The `stateen` registers at each level control access to state at all less-privileged levels, - but not at its own level. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in - that privilege mode an instruction that implicitly updates the state without reading it may - or may not raise an illegal instruction or virtual instruction exception. Such cases must - be disambiguated by being explicitly specified one way or the other. - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA - extensions that introduce the controlled state. - - Each bit of a supervisor-level `sstateen` CSR controls user-level access (from U-mode or VU-mode) - to an extension’s state. The intention is to allocate the bits of `sstateen` CSRs starting at the - least-significant end, bit 0, through to bit 31, and then on to the next-higher-numbered - `sstateen` CSR. + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not + deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. + + The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. + This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with + the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those + privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction + exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises + a virtual instruction exception instead of an illegal instruction exception. + + When this extension is not implemented, all state added by an extension is accessible as defined by that extension. + + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an + instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or + virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. + + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that + introduce the controlled state. + + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + + Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. + + Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that + hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` + CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` + and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit + appears as read-only zero in `sstateen` when accessed in VS-mode. + + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. + + On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these + values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros + too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to + allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor + is prepared to swap on a context switch, or to manage in some other way. + + For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 + of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; + etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. + + A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine + an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. + + Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over + accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. + + Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching + supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access + the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always + writable (not read-only). definedBy: allOf: From e5fa958fb5e7fa631b0261258a68609569d96541 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 1 May 2025 22:15:16 +0000 Subject: [PATCH 06/38] remove pre-commit-config.yaml from pr --- .pre-commit-config.yaml | 30 +----------------------------- 1 file changed, 1 insertion(+), 29 deletions(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index ec13c9d34..48e68fca8 100755 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -8,35 +8,24 @@ repos: rev: v5.0.0 hooks: - id: check-ast - stages: [pre-commit] - id: check-builtin-literals - stages: [pre-commit] - id: check-case-conflict - stages: [pre-commit] - id: check-docstring-first - stages: [pre-commit] - id: check-symlinks - stages: [pre-commit] - id: end-of-file-fixer - stages: [pre-commit] - id: trailing-whitespace - stages: [pre-commit] args: [--markdown-linebreak-ext=md] - id: check-merge-conflict - stages: [pre-commit] args: ["--assume-in-merge"] exclude: \.adoc$ # sections titles Level 6 "=======" get flagged otherwise - id: check-json - stages: [pre-commit] exclude: ^\.devcontainer/ # Uses JSONC (comments) - id: check-yaml - stages: [pre-commit] - repo: https://github.com/rbubley/mirrors-prettier rev: v3.5.3 hooks: - id: prettier - stages: [pre-commit] files: \.(json|toml|yml|yaml)$ exclude: schemas/json-schema-draft-07.json @@ -44,27 +33,22 @@ repos: rev: 0.33.0 hooks: - id: check-jsonschema - stages: [pre-commit] alias: check-jsonschema-inst files: ^arch/inst/.*\.(yaml|yml)$ args: ["--schemafile", "schemas/inst_schema.json"] - id: check-jsonschema - stages: [pre-commit] alias: check-jsonschema-csr files: ^arch/csr/.*\.(yaml|yml)$ args: ["--schemafile", "schemas/csr_schema.json"] - id: check-jsonschema - stages: [pre-commit] alias: check-jsonschema-ext files: ^arch/ext/.*\.(yaml|yml)$ args: ["--schemafile", "schemas/ext_schema.json"] - id: check-jsonschema - stages: [pre-commit] alias: check-jsonschema-cert-model files: ^arch/proc_cert_model/.*\.(yaml|yml)$ args: ["--schemafile", "schemas/proc_cert_model_schema.json"] - id: check-jsonschema - stages: [pre-commit] alias: check-jsonschema-cert-class files: ^arch/proc_cert_class/.*\.(yaml|yml)$ args: ["--schemafile", "schemas/proc_cert_class_schema.json"] @@ -78,7 +62,6 @@ repos: rev: "v20.1.0" hooks: - id: clang-format - stages: [pre-commit] types_or: [c++, c] files: \.(hpp|cpp)$ # TEMPORARILY DISABLE CLANG-FORMAT IN LIBHART @@ -88,13 +71,11 @@ repos: rev: 25.1.0 hooks: - id: black - stages: [pre-commit] - repo: https://github.com/asottile/pyupgrade rev: v3.19.1 hooks: - id: pyupgrade - stages: [pre-commit] - repo: local hooks: @@ -109,7 +90,6 @@ repos: rev: v3.11.0-1 hooks: - id: shfmt - stages: [pre-commit] args: - --indent - "2" @@ -118,12 +98,4 @@ repos: - repo: https://github.com/fsfe/reuse-tool rev: v5.0.2 hooks: - - id: reuse-lint-file - - - repo: https://github.com/alessandrojcm/commitlint-pre-commit-hook - rev: v9.22.0 - hooks: - - id: commitlint - stages: [commit-msg] - additional_dependencies: - - "@commitlint/config-conventional" + - id: reuse From fffabdaf82337c72209a44ae9e44a98cbbbcd200 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 1 May 2025 22:20:06 +0000 Subject: [PATCH 07/38] remove pre-commit file changes --- .pre-commit-config.yaml | 31 ++++++++++++++++++++++++++++++- 1 file changed, 30 insertions(+), 1 deletion(-) diff --git a/.pre-commit-config.yaml b/.pre-commit-config.yaml index 48e68fca8..9920b68d4 100755 --- a/.pre-commit-config.yaml +++ b/.pre-commit-config.yaml @@ -8,24 +8,35 @@ repos: rev: v5.0.0 hooks: - id: check-ast + stages: [pre-commit] - id: check-builtin-literals + stages: [pre-commit] - id: check-case-conflict + stages: [pre-commit] - id: check-docstring-first + stages: [pre-commit] - id: check-symlinks + stages: [pre-commit] - id: end-of-file-fixer + stages: [pre-commit] - id: trailing-whitespace + stages: [pre-commit] args: [--markdown-linebreak-ext=md] - id: check-merge-conflict + stages: [pre-commit] args: ["--assume-in-merge"] exclude: \.adoc$ # sections titles Level 6 "=======" get flagged otherwise - id: check-json + stages: [pre-commit] exclude: ^\.devcontainer/ # Uses JSONC (comments) - id: check-yaml + stages: [pre-commit] - repo: https://github.com/rbubley/mirrors-prettier rev: v3.5.3 hooks: - id: prettier + stages: [pre-commit] files: \.(json|toml|yml|yaml)$ exclude: schemas/json-schema-draft-07.json @@ -33,22 +44,27 @@ repos: rev: 0.33.0 hooks: - id: check-jsonschema + stages: [pre-commit] alias: check-jsonschema-inst files: ^arch/inst/.*\.(yaml|yml)$ args: ["--schemafile", "schemas/inst_schema.json"] - id: check-jsonschema + stages: [pre-commit] alias: check-jsonschema-csr files: ^arch/csr/.*\.(yaml|yml)$ args: ["--schemafile", "schemas/csr_schema.json"] - id: check-jsonschema + stages: [pre-commit] alias: check-jsonschema-ext files: ^arch/ext/.*\.(yaml|yml)$ args: ["--schemafile", "schemas/ext_schema.json"] - id: check-jsonschema + stages: [pre-commit] alias: check-jsonschema-cert-model files: ^arch/proc_cert_model/.*\.(yaml|yml)$ args: ["--schemafile", "schemas/proc_cert_model_schema.json"] - id: check-jsonschema + stages: [pre-commit] alias: check-jsonschema-cert-class files: ^arch/proc_cert_class/.*\.(yaml|yml)$ args: ["--schemafile", "schemas/proc_cert_class_schema.json"] @@ -62,6 +78,7 @@ repos: rev: "v20.1.0" hooks: - id: clang-format + stages: [pre-commit] types_or: [c++, c] files: \.(hpp|cpp)$ # TEMPORARILY DISABLE CLANG-FORMAT IN LIBHART @@ -71,11 +88,13 @@ repos: rev: 25.1.0 hooks: - id: black + stages: [pre-commit] - repo: https://github.com/asottile/pyupgrade rev: v3.19.1 hooks: - id: pyupgrade + stages: [pre-commit] - repo: local hooks: @@ -90,6 +109,7 @@ repos: rev: v3.11.0-1 hooks: - id: shfmt + stages: [pre-commit] args: - --indent - "2" @@ -98,4 +118,13 @@ repos: - repo: https://github.com/fsfe/reuse-tool rev: v5.0.2 hooks: - - id: reuse + - id: reuse-lint-file + exclude: COMMIT_EDITMSG|MERGE_MSG + + - repo: https://github.com/alessandrojcm/commitlint-pre-commit-hook + rev: v9.22.0 + hooks: + - id: commitlint + stages: [commit-msg] + additional_dependencies: + - "@commitlint/config-conventional" From 354ed45593050c85634f824a5ad19a34705a4310 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 1 May 2025 22:52:35 +0000 Subject: [PATCH 08/38] add definedBy for fields --- arch/csr/hstateen0.yaml | 11 +++++++++++ arch/csr/hstateen0h.yaml | 8 ++++++++ arch/csr/hstateen1.yaml | 1 + arch/csr/hstateen1h.yaml | 1 + arch/csr/hstateen2.yaml | 1 + arch/csr/hstateen2h.yaml | 1 + arch/csr/hstateen3.yaml | 1 + arch/csr/hstateen3h.yaml | 1 + arch/csr/mstateen0.yaml | 10 ++++++++++ arch/csr/mstateen0h.yaml | 7 +++++++ arch/csr/sstateen0.yaml | 3 +++ 11 files changed, 45 insertions(+) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 0d8a8c1b4..67296f0d2 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -65,6 +65,7 @@ definedBy: - Ssstateen fields: SE0: + long_name: sstateen0 access control location: 63 base: 64 description: | @@ -73,6 +74,9 @@ fields: reset_value: UNDEFINED_LEGAL ENVCFG: location: 62 + definedBy: + name: S + version: ">= 1.11" base: 64 description: | The ENVCFG bit in `hstateen0` controls access to the `senvcfg` CSRs. @@ -80,6 +84,7 @@ fields: reset_value: UNDEFINED_LEGAL CSRIND: location: 60 + definedBy: Sscsrind base: 64 description: | The CSRIND bit in `hstateen0` controls access to the `siselect` and the @@ -89,6 +94,7 @@ fields: reset_value: UNDEFINED_LEGAL AIA: location: 59 + definedBy: Ssaia base: 64 description: | The AIA bit in `hstateen0` controls access to all state introduced by @@ -98,6 +104,7 @@ fields: reset_value: UNDEFINED_LEGAL IMSIC: location: 58 + definedBy: Ssaia base: 64 description: | The IMSIC bit in `hstateen0` controls access to the guest IMSIC state, @@ -109,6 +116,7 @@ fields: reset_value: UNDEFINED_LEGAL CONTEXT: location: 57 + definedBy: Sdtrig base: 64 description: | The CONTEXT bit in `hstateen0` controls access to the `scontext` CSR provided @@ -117,12 +125,15 @@ fields: reset_value: UNDEFINED_LEGAL JVT: location: 2 + definedBy: Zcmt description: | The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW reset_value: UNDEFINED_LEGAL FCSR: location: 1 + definedBy: + anyOf: [Zfinx, Zdinx] description: | The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related diff --git a/arch/csr/hstateen0h.yaml b/arch/csr/hstateen0h.yaml index 3782ccfc6..54f559fc0 100644 --- a/arch/csr/hstateen0h.yaml +++ b/arch/csr/hstateen0h.yaml @@ -25,6 +25,7 @@ definedBy: - Ssstateen fields: SE0: + long_name: sstateen0 access control location: 31 description: | The SE0 bit in `hstateen0h` controls access to the `sstateen0` CSR. @@ -32,12 +33,16 @@ fields: reset_value: UNDEFINED_LEGAL ENVCFG: location: 30 + definedBy: + name: S + version: ">= 1.11" description: | The ENVCFG bit in `hstateen0h` controls access to the `senvcfg` CSRs. type: RW reset_value: UNDEFINED_LEGAL CSRIND: location: 28 + definedBy: Sscsrind description: | The CSRIND bit in `hstateen0h` controls access to the `siselect` and the `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind @@ -46,6 +51,7 @@ fields: reset_value: UNDEFINED_LEGAL AIA: location: 27 + definedBy: Ssaia description: | The AIA bit in `hstateen0h` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the @@ -54,6 +60,7 @@ fields: reset_value: UNDEFINED_LEGAL IMSIC: location: 26 + definedBy: Ssaia description: | The IMSIC bit in `hstateen0h` controls access to the guest IMSIC state, including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension. @@ -64,6 +71,7 @@ fields: reset_value: UNDEFINED_LEGAL CONTEXT: location: 25 + definedBy: Sdtrig description: | The CONTEXT bit in `hstateen0h` controls access to the `scontext` CSR provided by the Sdtrig extension. diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index ac80243ae..b59425601 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -65,6 +65,7 @@ definedBy: - Ssstateen fields: SE0: + long_name: sstateen1 access control location: 63 base: 64 description: | diff --git a/arch/csr/hstateen1h.yaml b/arch/csr/hstateen1h.yaml index 14b4eae18..c8952735b 100644 --- a/arch/csr/hstateen1h.yaml +++ b/arch/csr/hstateen1h.yaml @@ -25,6 +25,7 @@ definedBy: - Ssstateen fields: SE0: + long_name: sstateen1 access control location: 31 description: | The SE0 bit in `hstateen1h` controls access to the `sstateen1` CSR. diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index b26edfe1a..c6559b7e4 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -65,6 +65,7 @@ definedBy: - Ssstateen fields: SE0: + long_name: sstateen2 access control location: 63 base: 64 description: | diff --git a/arch/csr/hstateen2h.yaml b/arch/csr/hstateen2h.yaml index 13e08613a..82820a7ff 100644 --- a/arch/csr/hstateen2h.yaml +++ b/arch/csr/hstateen2h.yaml @@ -25,6 +25,7 @@ definedBy: - Ssstateen fields: SE0: + long_name: sstateen2 access control location: 31 description: | The SE0 bit in `hstateen2h` controls access to the `sstateen2` CSR. diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index 99e682fae..bcf9b78f7 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -65,6 +65,7 @@ definedBy: - Ssstateen fields: SE0: + long_name: sstateen3 access control location: 63 base: 64 description: | diff --git a/arch/csr/hstateen3h.yaml b/arch/csr/hstateen3h.yaml index 6785303a8..ab47093d0 100644 --- a/arch/csr/hstateen3h.yaml +++ b/arch/csr/hstateen3h.yaml @@ -25,6 +25,7 @@ definedBy: - Ssstateen fields: SE0: + long_name: sstateen3 access control location: 31 description: | The SE0 bit in `hstateen3h` controls access to the `sstateen3` CSR. diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index 2bcf4a860..3a04d7938 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -76,6 +76,9 @@ fields: reset_value: UNDEFINED_LEGAL ENVCFG: location: 62 + definedBy: + name: S + version: ">= 1.11" base: 64 description: | The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs. @@ -83,6 +86,7 @@ fields: reset_value: UNDEFINED_LEGAL CSRIND: location: 60 + definedBy: Sscsrind base: 64 description: | The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` @@ -91,6 +95,7 @@ fields: reset_value: UNDEFINED_LEGAL AIA: location: 59 + definedBy: Ssaia base: 64 description: | The AIA bit in `mstateen0` controls access to all state introduced by the Ssaia extension and is not @@ -99,6 +104,7 @@ fields: reset_value: UNDEFINED_LEGAL IMSIC: location: 58 + definedBy: Ssaia base: 64 description: | The IMSIC bit in `mstateen0` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, @@ -107,6 +113,7 @@ fields: reset_value: UNDEFINED_LEGAL CONTEXT: location: 57 + definedBy: Sdtrig base: 64 description: | The CONTEXT bit in `mstateen0` controls access to the `scontext` and `hcontext` CSRs provided by the @@ -123,12 +130,15 @@ fields: reset_value: UNDEFINED_LEGAL JVT: location: 2 + definedBy: Zcmt description: | The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW reset_value: UNDEFINED_LEGAL FCSR: location: 1 + definedBy: + anyOf: [Zfinx, Zdinx] description: | The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml index 9d00b3cb8..27dd4faf1 100644 --- a/arch/csr/mstateen0h.yaml +++ b/arch/csr/mstateen0h.yaml @@ -23,12 +23,16 @@ fields: reset_value: UNDEFINED_LEGAL ENVCFG: location: 30 + definedBy: + name: S + version: ">= 1.11" description: | The ENVCFG bit in `mstateen0h` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs. type: RW reset_value: UNDEFINED_LEGAL CSRIND: location: 28 + definedBy: Sscsrind description: | The CSRIND bit in `mstateen0h` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions. @@ -36,6 +40,7 @@ fields: reset_value: UNDEFINED_LEGAL AIA: location: 27 + definedBy: Ssaia description: | The AIA bit in `mstateen0h` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits. @@ -43,6 +48,7 @@ fields: reset_value: UNDEFINED_LEGAL IMSIC: location: 26 + definedBy: Ssaia description: | The IMSIC bit in `mstateen0h` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, provided by the Ssaia extension. @@ -50,6 +56,7 @@ fields: reset_value: UNDEFINED_LEGAL CONTEXT: location: 25 + definedBy: Sdtrig description: | The CONTEXT bit in `mstateen0h` controls access to the `scontext` and `hcontext` CSRs provided by the Sdtrig extension. diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index ba5d67f9d..202dae8d8 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -78,12 +78,15 @@ definedBy: fields: JVT: location: 2 + definedBy: Zcmt description: | The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW reset_value: UNDEFINED_LEGAL FCSR: location: 1 + definedBy: + anyOf: [Zfinx, Zdinx] description: | The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related From 94847896a2ff4259a3fd89434addce558b7c05df Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 1 May 2025 23:07:40 +0000 Subject: [PATCH 09/38] add sw_write and sw_read for alias --- arch/csr/hstateen0h.yaml | 25 +++++++++++++++++++++++++ arch/csr/hstateen1h.yaml | 5 +++++ arch/csr/hstateen2h.yaml | 5 +++++ arch/csr/hstateen3h.yaml | 5 +++++ arch/csr/mstateen0h.yaml | 29 +++++++++++++++++++++++++++++ arch/csr/mstateen1h.yaml | 5 +++++ arch/csr/mstateen2h.yaml | 5 +++++ arch/csr/mstateen3h.yaml | 5 +++++ 8 files changed, 84 insertions(+) diff --git a/arch/csr/hstateen0h.yaml b/arch/csr/hstateen0h.yaml index 54f559fc0..e261a1641 100644 --- a/arch/csr/hstateen0h.yaml +++ b/arch/csr/hstateen0h.yaml @@ -27,6 +27,10 @@ fields: SE0: long_name: sstateen0 access control location: 31 + alias: hstateen0.SE0 + sw_write(csr_value): | + CSR[hstateen0].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `hstateen0h` controls access to the `sstateen0` CSR. type: RW @@ -36,6 +40,10 @@ fields: definedBy: name: S version: ">= 1.11" + alias: hstateen0.ENVCFG + sw_write(csr_value): | + CSR[hstateen0].ENVCFG = csr_value.ENVCFG; + return csr_value.ENVCFG; description: | The ENVCFG bit in `hstateen0h` controls access to the `senvcfg` CSRs. type: RW @@ -43,6 +51,10 @@ fields: CSRIND: location: 28 definedBy: Sscsrind + alias: hstateen0.CSRIND + sw_write(csr_value): | + CSR[hstateen0].CSRIND = csr_value.CSRIND; + return csr_value.CSRIND; description: | The CSRIND bit in `hstateen0h` controls access to the `siselect` and the `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind @@ -52,6 +64,10 @@ fields: AIA: location: 27 definedBy: Ssaia + alias: hstateen0.AIA + sw_write(csr_value): | + CSR[hstateen0].AIA = csr_value.AIA; + return csr_value.AIA; description: | The AIA bit in `hstateen0h` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the @@ -61,6 +77,10 @@ fields: IMSIC: location: 26 definedBy: Ssaia + alias: hstateen0.IMSIC + sw_write(csr_value): | + CSR[hstateen0].IMSIC = csr_value.IMSIC; + return csr_value.IMSIC; description: | The IMSIC bit in `hstateen0h` controls access to the guest IMSIC state, including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension. @@ -72,8 +92,13 @@ fields: CONTEXT: location: 25 definedBy: Sdtrig + alias: hstateen0.CONTEXT + sw_write(csr_value): | + CSR[hstateen0].CONTEXT = csr_value.CONTEXT; + return csr_value.CONTEXT; description: | The CONTEXT bit in `hstateen0h` controls access to the `scontext` CSR provided by the Sdtrig extension. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): return $bits(CSR[hstateen0])[63:32]; diff --git a/arch/csr/hstateen1h.yaml b/arch/csr/hstateen1h.yaml index c8952735b..f321dbb3b 100644 --- a/arch/csr/hstateen1h.yaml +++ b/arch/csr/hstateen1h.yaml @@ -27,7 +27,12 @@ fields: SE0: long_name: sstateen1 access control location: 31 + alias: hstateen1.SE0 + sw_write(csr_value): | + CSR[hstateen1].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `hstateen1h` controls access to the `sstateen1` CSR. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): return $bits(CSR[hstateen1])[63:32]; diff --git a/arch/csr/hstateen2h.yaml b/arch/csr/hstateen2h.yaml index 82820a7ff..f85cb115a 100644 --- a/arch/csr/hstateen2h.yaml +++ b/arch/csr/hstateen2h.yaml @@ -27,7 +27,12 @@ fields: SE0: long_name: sstateen2 access control location: 31 + alias: hstateen2.SE0 + sw_write(csr_value): | + CSR[hstateen2].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `hstateen2h` controls access to the `sstateen2` CSR. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): return $bits(CSR[hstateen2])[63:32]; diff --git a/arch/csr/hstateen3h.yaml b/arch/csr/hstateen3h.yaml index ab47093d0..2026259d8 100644 --- a/arch/csr/hstateen3h.yaml +++ b/arch/csr/hstateen3h.yaml @@ -27,7 +27,12 @@ fields: SE0: long_name: sstateen3 access control location: 31 + alias: hstateen3.SE0 + sw_write(csr_value): | + CSR[hstateen3].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `hstateen3h` controls access to the `sstateen3` CSR. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): return $bits(CSR[hstateen3])[63:32]; diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml index 27dd4faf1..beae56f15 100644 --- a/arch/csr/mstateen0h.yaml +++ b/arch/csr/mstateen0h.yaml @@ -17,6 +17,10 @@ definedBy: Smstateen fields: SE0: location: 31 + alias: mstateen0.SE0 + sw_write(csr_value): | + CSR[mstateen0].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `mstateen0h` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs. type: RW @@ -26,6 +30,10 @@ fields: definedBy: name: S version: ">= 1.11" + alias: mstateen0.ENVCFG + sw_write(csr_value): | + CSR[mstateen0].ENVCFG = csr_value.ENVCFG; + return csr_value.ENVCFG; description: | The ENVCFG bit in `mstateen0h` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs. type: RW @@ -33,6 +41,10 @@ fields: CSRIND: location: 28 definedBy: Sscsrind + alias: mstateen0.CSRIND + sw_write(csr_value): | + CSR[mstateen0].CSRIND = csr_value.CSRIND; + return csr_value.CSRIND; description: | The CSRIND bit in `mstateen0h` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions. @@ -41,6 +53,10 @@ fields: AIA: location: 27 definedBy: Ssaia + alias: mstateen0.AIA + sw_write(csr_value): | + CSR[mstateen0].AIA = csr_value.AIA; + return csr_value.AIA; description: | The AIA bit in `mstateen0h` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits. @@ -49,6 +65,10 @@ fields: IMSIC: location: 26 definedBy: Ssaia + alias: mstateen0.IMSIC + sw_write(csr_value): | + CSR[mstateen0].IMSIC = csr_value.IMSIC; + return csr_value.IMSIC; description: | The IMSIC bit in `mstateen0h` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, provided by the Ssaia extension. @@ -57,6 +77,10 @@ fields: CONTEXT: location: 25 definedBy: Sdtrig + alias: mstateen0.CONTEXT + sw_write(csr_value): | + CSR[mstateen0].CONTEXT = csr_value.CONTEXT; + return csr_value.CONTEXT; description: | The CONTEXT bit in `mstateen0h` controls access to the `scontext` and `hcontext` CSRs provided by the Sdtrig extension. @@ -64,8 +88,13 @@ fields: reset_value: UNDEFINED_LEGAL P1P13: location: 24 + alias: mstateen0.P1P13 + sw_write(csr_value): | + CSR[mstateen0].P1P13 = csr_value.P1P13; + return csr_value.P1P13; description: | The P1P13 bit in `mstateen0h` controls access to the `hedelegh` introduced by Privileged Specification Version 1.13. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): return $bits(CSR[mstateen0])[63:32]; diff --git a/arch/csr/mstateen1h.yaml b/arch/csr/mstateen1h.yaml index f478323b9..a0ce6cd8c 100644 --- a/arch/csr/mstateen1h.yaml +++ b/arch/csr/mstateen1h.yaml @@ -17,7 +17,12 @@ definedBy: Smstateen fields: SE0: location: 31 + alias: mstateen1.SE0 + sw_write(csr_value): | + CSR[mstateen1].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `mstateen1h` controls access to the `hstateen1`, `hstateen1h`, and the `sstateen1` CSRs. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): return $bits(CSR[mstateen1])[63:32]; diff --git a/arch/csr/mstateen2h.yaml b/arch/csr/mstateen2h.yaml index ccad4f6e3..aa68a7562 100644 --- a/arch/csr/mstateen2h.yaml +++ b/arch/csr/mstateen2h.yaml @@ -17,7 +17,12 @@ definedBy: Smstateen fields: SE0: location: 31 + alias: mstateen2.SE0 + sw_write(csr_value): | + CSR[mstateen2].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `mstateen2h` controls access to the `hstateen2`, `hstateen2h`, and the `sstateen2` CSRs. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): return $bits(CSR[mstateen2])[63:32]; diff --git a/arch/csr/mstateen3h.yaml b/arch/csr/mstateen3h.yaml index 0a9fed075..969f3df72 100644 --- a/arch/csr/mstateen3h.yaml +++ b/arch/csr/mstateen3h.yaml @@ -17,7 +17,12 @@ definedBy: Smstateen fields: SE0: location: 31 + alias: mstateen3.SE0 + sw_write(csr_value): | + CSR[mstateen3].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `mstateen3h` controls access to the `hstateen3`, `hstateen3h`, and the `sstateen3` CSRs. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): return $bits(CSR[mstateen3])[63:32]; From 493e97c8894da0975bc4af969c7cb0e2d824390a Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Mon, 5 May 2025 16:39:48 +0000 Subject: [PATCH 10/38] add long names --- arch/csr/hstateen0.yaml | 8 ++++++++ arch/csr/hstateen0h.yaml | 5 +++++ arch/csr/mstateen0.yaml | 10 ++++++++++ arch/csr/mstateen0h.yaml | 7 +++++++ arch/csr/mstateen1.yaml | 1 + arch/csr/mstateen1h.yaml | 1 + arch/csr/mstateen2.yaml | 1 + arch/csr/mstateen2h.yaml | 1 + arch/csr/mstateen3.yaml | 1 + arch/csr/mstateen3h.yaml | 1 + arch/csr/sstateen0.yaml | 3 +++ 11 files changed, 39 insertions(+) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 67296f0d2..5550cd93f 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -73,6 +73,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL ENVCFG: + long_name: senvcfg access control location: 62 definedBy: name: S @@ -83,6 +84,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL CSRIND: + long_name: siselect and sireg* access control location: 60 definedBy: Sscsrind base: 64 @@ -93,6 +95,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL AIA: + long_name: Ssaia state access control location: 59 definedBy: Ssaia base: 64 @@ -103,6 +106,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL IMSIC: + long_name: IMSIC state access control location: 58 definedBy: Ssaia base: 64 @@ -115,6 +119,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL CONTEXT: + long_name: scontext access control location: 57 definedBy: Sdtrig base: 64 @@ -124,6 +129,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL JVT: + long_name: jvt access control location: 2 definedBy: Zcmt description: | @@ -131,6 +137,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL FCSR: + long_name: fcsr access control location: 1 definedBy: anyOf: [Zfinx, Zdinx] @@ -146,6 +153,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL C: + long_name: custom state access control location: 0 description: | The C bit controls access to any and all custom state. This bit is not custom state itself. diff --git a/arch/csr/hstateen0h.yaml b/arch/csr/hstateen0h.yaml index e261a1641..eee33014e 100644 --- a/arch/csr/hstateen0h.yaml +++ b/arch/csr/hstateen0h.yaml @@ -36,6 +36,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL ENVCFG: + long_name: senvcfg access control location: 30 definedBy: name: S @@ -49,6 +50,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL CSRIND: + long_name: siselect and sireg* access control location: 28 definedBy: Sscsrind alias: hstateen0.CSRIND @@ -62,6 +64,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL AIA: + long_name: Ssaia state access control location: 27 definedBy: Ssaia alias: hstateen0.AIA @@ -75,6 +78,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL IMSIC: + long_name: IMSIC state access control location: 26 definedBy: Ssaia alias: hstateen0.IMSIC @@ -90,6 +94,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL CONTEXT: + long_name: scontext access control location: 25 definedBy: Sdtrig alias: hstateen0.CONTEXT diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index 3a04d7938..dfade14b9 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -68,6 +68,7 @@ description: | definedBy: Smstateen fields: SE0: + long_name: hstateen0, hstateen0h, and sstateen0 access control location: 63 base: 64 description: | @@ -75,6 +76,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL ENVCFG: + long_name: henvcfg, henvcfgh, and senvcfg access control location: 62 definedBy: name: S @@ -85,6 +87,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL CSRIND: + long_name: siselect, sireg*, vsiselect, and vsireg* access control location: 60 definedBy: Sscsrind base: 64 @@ -94,6 +97,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL AIA: + long_name: Ssaia state access control location: 59 definedBy: Ssaia base: 64 @@ -103,6 +107,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL IMSIC: + long_name: IMSIC state access control location: 58 definedBy: Ssaia base: 64 @@ -112,6 +117,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL CONTEXT: + long_name: scontext and hcontext access control location: 57 definedBy: Sdtrig base: 64 @@ -121,6 +127,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL P1P13: + long_name: hedelegh access control location: 56 base: 64 description: | @@ -129,6 +136,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL JVT: + long_name: jvt access control location: 2 definedBy: Zcmt description: | @@ -136,6 +144,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL FCSR: + long_name: fcsr access control location: 1 definedBy: anyOf: [Zfinx, Zdinx] @@ -151,6 +160,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL C: + long_name: custom state access control location: 0 description: | The C bit controls access to any and all custom state. This bit is not custom state itself. The C bit of diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml index beae56f15..8645f0e2c 100644 --- a/arch/csr/mstateen0h.yaml +++ b/arch/csr/mstateen0h.yaml @@ -16,6 +16,7 @@ description: | definedBy: Smstateen fields: SE0: + long_name: hstateen0, hstateen0h, and sstateen0 access control location: 31 alias: mstateen0.SE0 sw_write(csr_value): | @@ -26,6 +27,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL ENVCFG: + long_name: henvcfg, henvcfgh, and senvcfg access control location: 30 definedBy: name: S @@ -39,6 +41,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL CSRIND: + long_name: siselect, sireg*, vsiselect, and vsireg* access control location: 28 definedBy: Sscsrind alias: mstateen0.CSRIND @@ -51,6 +54,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL AIA: + long_name: Ssaia state access control location: 27 definedBy: Ssaia alias: mstateen0.AIA @@ -63,6 +67,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL IMSIC: + long_name: IMSIC state access control location: 26 definedBy: Ssaia alias: mstateen0.IMSIC @@ -75,6 +80,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL CONTEXT: + long_name: scontext and hcontext access control location: 25 definedBy: Sdtrig alias: mstateen0.CONTEXT @@ -87,6 +93,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL P1P13: + long_name: hedelegh access control location: 24 alias: mstateen0.P1P13 sw_write(csr_value): | diff --git a/arch/csr/mstateen1.yaml b/arch/csr/mstateen1.yaml index 55b7d4ed0..8e213044f 100644 --- a/arch/csr/mstateen1.yaml +++ b/arch/csr/mstateen1.yaml @@ -68,6 +68,7 @@ description: | definedBy: Smstateen fields: SE0: + long_name: hstateen1, hstateen1h, and sstateen1 access control location: 63 base: 64 description: | diff --git a/arch/csr/mstateen1h.yaml b/arch/csr/mstateen1h.yaml index a0ce6cd8c..bcba1dc38 100644 --- a/arch/csr/mstateen1h.yaml +++ b/arch/csr/mstateen1h.yaml @@ -16,6 +16,7 @@ description: | definedBy: Smstateen fields: SE0: + long_name: hstateen1, hstateen1h, and sstateen1 access control location: 31 alias: mstateen1.SE0 sw_write(csr_value): | diff --git a/arch/csr/mstateen2.yaml b/arch/csr/mstateen2.yaml index b82c1c440..47ee83c09 100644 --- a/arch/csr/mstateen2.yaml +++ b/arch/csr/mstateen2.yaml @@ -68,6 +68,7 @@ description: | definedBy: Smstateen fields: SE0: + long_name: hstateen2, hstateen2h, and sstateen2 access control location: 63 base: 64 description: | diff --git a/arch/csr/mstateen2h.yaml b/arch/csr/mstateen2h.yaml index aa68a7562..5b19e2923 100644 --- a/arch/csr/mstateen2h.yaml +++ b/arch/csr/mstateen2h.yaml @@ -16,6 +16,7 @@ description: | definedBy: Smstateen fields: SE0: + long_name: hstateen2, hstateen2h, and sstateen2 access control location: 31 alias: mstateen2.SE0 sw_write(csr_value): | diff --git a/arch/csr/mstateen3.yaml b/arch/csr/mstateen3.yaml index 50405cce0..df4c61344 100644 --- a/arch/csr/mstateen3.yaml +++ b/arch/csr/mstateen3.yaml @@ -68,6 +68,7 @@ description: | definedBy: Smstateen fields: SE0: + long_name: hstateen3, hstateen3h, and sstateen3 access control location: 63 base: 64 description: | diff --git a/arch/csr/mstateen3h.yaml b/arch/csr/mstateen3h.yaml index 969f3df72..ed2864555 100644 --- a/arch/csr/mstateen3h.yaml +++ b/arch/csr/mstateen3h.yaml @@ -16,6 +16,7 @@ description: | definedBy: Smstateen fields: SE0: + long_name: hstateen3, hstateen3h, and sstateen3 access control location: 31 alias: mstateen3.SE0 sw_write(csr_value): | diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index 202dae8d8..814792949 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -77,6 +77,7 @@ definedBy: - Ssstateen fields: JVT: + long_name: jvt access control location: 2 definedBy: Zcmt description: | @@ -84,6 +85,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL FCSR: + long_name: fcsr access control location: 1 definedBy: anyOf: [Zfinx, Zdinx] @@ -99,6 +101,7 @@ fields: type: RW reset_value: UNDEFINED_LEGAL C: + long_name: custom state access control location: 0 description: | The C bit controls access to any and all custom state. This bit is not custom state itself. The C bit of From 843c1c666825db2438f009b8779125af63cb183f Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Mon, 5 May 2025 17:32:37 +0000 Subject: [PATCH 11/38] structured format descriptions --- arch/csr/hstateen0.yaml | 95 +++++++++++++++----------------- arch/csr/hstateen1.yaml | 95 +++++++++++++++----------------- arch/csr/hstateen2.yaml | 95 +++++++++++++++----------------- arch/csr/hstateen3.yaml | 95 +++++++++++++++----------------- arch/csr/mstateen0.yaml | 112 +++++++++++++++++++------------------ arch/csr/mstateen1.yaml | 112 +++++++++++++++++++------------------ arch/csr/mstateen2.yaml | 112 +++++++++++++++++++------------------ arch/csr/mstateen3.yaml | 112 +++++++++++++++++++------------------ arch/csr/sstateen0.yaml | 119 +++++++++++++++++++--------------------- arch/csr/sstateen1.yaml | 119 +++++++++++++++++++--------------------- arch/csr/sstateen2.yaml | 119 +++++++++++++++++++--------------------- arch/csr/sstateen3.yaml | 119 +++++++++++++++++++--------------------- 12 files changed, 624 insertions(+), 680 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 5550cd93f..8b3121a04 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -7,56 +7,51 @@ long_name: Hypervisor State Enable 0 Register address: 0x60C priv_mode: S length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling - accesses for a virtual machine (from VS and VU modes). - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine - an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. - - Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over - accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. +description: + - id: csr-hstateen0-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-hstateen0-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-hstateen0-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-hstateen0-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-hstateen0-encodings + normative: true + text: | + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, + except controlling accesses for a virtual machine (from VS and VU modes). + - id: csr-hstateen0-zero + normative: true + text: | + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + - id: csr-hstateen0-read-only + normative: true + text: | + A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one + in the matching `mstateen` CSR. definedBy: allOf: diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index b59425601..40294535d 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -7,56 +7,51 @@ long_name: Hypervisor State Enable 1 Register address: 0x60D priv_mode: S length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling - accesses for a virtual machine (from VS and VU modes). - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine - an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. - - Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over - accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. +description: + - id: csr-hstateen1-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-hstateen1-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-hstateen1-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-hstateen1-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-hstateen1-encodings + normative: true + text: | + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, + except controlling accesses for a virtual machine (from VS and VU modes). + - id: csr-hstateen1-zero + normative: true + text: | + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + - id: csr-hstateen1-read-only + normative: true + text: | + A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one + in the matching `mstateen` CSR. definedBy: allOf: diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index c6559b7e4..f43616a7e 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -7,56 +7,51 @@ long_name: Hypervisor State Enable 2 Register address: 0x60E priv_mode: S length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling - accesses for a virtual machine (from VS and VU modes). - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine - an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. - - Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over - accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. +description: + - id: csr-hstateen2-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-hstateen2-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-hstateen2-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-hstateen2-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-hstateen2-encodings + normative: true + text: | + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, + except controlling accesses for a virtual machine (from VS and VU modes). + - id: csr-hstateen2-zero + normative: true + text: | + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + - id: csr-hstateen2-read-only + normative: true + text: | + A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one + in the matching `mstateen` CSR. definedBy: allOf: diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index bcf9b78f7..f53609100 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -7,56 +7,51 @@ long_name: Hypervisor State Enable 3 Register address: 0x60F priv_mode: S length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, except controlling - accesses for a virtual machine (from VS and VU modes). - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine - an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. - - Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over - accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. +description: + - id: csr-hstateen3-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-hstateen3-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-hstateen3-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-hstateen3-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-hstateen3-encodings + normative: true + text: | + With the hypervisor extension, the `hstateen` CSRs have identical encodings to the `mstateen` CSRs, + except controlling accesses for a virtual machine (from VS and VU modes). + - id: csr-hstateen3-zero + normative: true + text: | + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + - id: csr-hstateen3-read-only + normative: true + text: | + A bit in an `hstateen` CSR cannot be read-only one unless the same bit is read-only one + in the matching `mstateen` CSR. definedBy: allOf: diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index dfade14b9..69ab46c02 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -7,63 +7,61 @@ long_name: Machine State Enable 0 Register address: 0x30C priv_mode: M length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching - `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an - `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently - inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are - applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, - through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated - from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant - end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher - `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in - the matching `sstateen` CSRs. - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching - supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access - the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always - writable (not read-only). +description: + - id: csr-mstateen0-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-mstateen0-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-mstateen0-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-mstateen0-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-mstateen0-bit-allocation + normative: true + text: | + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + - id: csr-mstateen0-zero + normative: true + text: | + For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs. + - id: csr-mstateen0-read-only + normative: true + text: | + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if + the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros. definedBy: Smstateen fields: diff --git a/arch/csr/mstateen1.yaml b/arch/csr/mstateen1.yaml index 8e213044f..6a727286b 100644 --- a/arch/csr/mstateen1.yaml +++ b/arch/csr/mstateen1.yaml @@ -7,63 +7,61 @@ long_name: Machine State Enable 1 Register address: 0x30D priv_mode: M length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching - `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an - `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently - inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are - applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, - through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated - from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant - end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher - `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in - the matching `sstateen` CSRs. - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching - supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access - the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always - writable (not read-only). +description: + - id: csr-mstateen1-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-mstateen1-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-mstateen1-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-mstateen1-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-mstateen1-bit-allocation + normative: true + text: | + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + - id: csr-mstateen1-zero + normative: true + text: | + For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs. + - id: csr-mstateen1-read-only + normative: true + text: | + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if + the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros. definedBy: Smstateen fields: diff --git a/arch/csr/mstateen2.yaml b/arch/csr/mstateen2.yaml index 47ee83c09..59140ee2a 100644 --- a/arch/csr/mstateen2.yaml +++ b/arch/csr/mstateen2.yaml @@ -7,63 +7,61 @@ long_name: Machine State Enable 2 Register address: 0x30E priv_mode: M length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching - `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an - `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently - inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are - applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, - through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated - from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant - end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher - `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in - the matching `sstateen` CSRs. - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching - supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access - the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always - writable (not read-only). +description: + - id: csr-mstateen2-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-mstateen2-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-mstateen2-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-mstateen2-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-mstateen2-bit-allocation + normative: true + text: | + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + - id: csr-mstateen2-zero + normative: true + text: | + For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs. + - id: csr-mstateen2-read-only + normative: true + text: | + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if + the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros. definedBy: Smstateen fields: diff --git a/arch/csr/mstateen3.yaml b/arch/csr/mstateen3.yaml index df4c61344..608ff6eea 100644 --- a/arch/csr/mstateen3.yaml +++ b/arch/csr/mstateen3.yaml @@ -7,63 +7,61 @@ long_name: Machine State Enable 3 Register address: 0x30F priv_mode: M length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching - `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an - `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently - inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are - applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, - through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated - from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant - end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher - `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in - the matching `sstateen` CSRs. - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching - supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access - the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always - writable (not read-only). +description: + - id: csr-mstateen3-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + or an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-mstateen3-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-mstateen3-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-mstateen3-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-mstateen3-bit-allocation + normative: true + text: | + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + - id: csr-mstateen3-zero + normative: true + text: | + For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs. + - id: csr-mstateen3-read-only + normative: true + text: | + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless + the same bit is read-only one in the matching `mstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero only if + the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros. definedBy: Smstateen fields: diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index 814792949..5fbd14c04 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -7,69 +7,62 @@ long_name: Supervisor State Enable 0 Register address: 0x10C priv_mode: S length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching - `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an - `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently - inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are - applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, - through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated - from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant - end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher - `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in - the matching `sstateen` CSRs. - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine - an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. - - Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over - accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. - - Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching - supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access - the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always - writable (not read-only). +description: + - id: csr-sstateen0-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-sstateen0-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-sstateen0-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-sstateen0-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-sstateen0-bit-allocation + normative: true + text: | + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + - id: csr-sstateen0-zero + normative: true + text: | + For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs. + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + - id: csr-sstateen0-read-only + normative: true + text: | + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero + only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros. definedBy: allOf: diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index 5afd4e46f..d189230b2 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -7,69 +7,62 @@ long_name: Supervisor State Enable 1 Register address: 0x10D priv_mode: S length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching - `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an - `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently - inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are - applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, - through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated - from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant - end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher - `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in - the matching `sstateen` CSRs. - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine - an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. - - Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over - accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. - - Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching - supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access - the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always - writable (not read-only). +description: + - id: csr-sstateen1-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-sstateen1-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-sstateen1-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-sstateen1-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-sstateen1-bit-allocation + normative: true + text: | + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + - id: csr-sstateen1-zero + normative: true + text: | + For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs. + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + - id: csr-sstateen1-read-only + normative: true + text: | + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero + only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros. definedBy: allOf: diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index e753d8dff..8a251bb1d 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -7,69 +7,62 @@ long_name: Supervisor State Enable 2 Register address: 0x10E priv_mode: S length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching - `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an - `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently - inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are - applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, - through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated - from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant - end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher - `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in - the matching `sstateen` CSRs. - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine - an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. - - Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over - accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. - - Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching - supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access - the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always - writable (not read-only). +description: + - id: csr-sstateen2-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-sstateen2-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-sstateen2-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-sstateen2-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-sstateen2-bit-allocation + normative: true + text: | + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + - id: csr-sstateen2-zero + normative: true + text: | + For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs. + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + - id: csr-sstateen2-read-only + normative: true + text: | + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero + only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros. definedBy: allOf: diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index a767874da..d8a76689c 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -7,69 +7,62 @@ long_name: Supervisor State Enable 3 Register address: 0x10F priv_mode: S length: MXLEN -description: | - Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, for an extension that was not - deemed "worthy" of a full XS field in `sstatus` like the FS and VS fields for the F and V extensions. - - The `stateen` registers at each level control access to state at all less-privileged levels, but not at its own level. - This is analogous to how the existing `counteren` CSRs control access to performance counter registers. Just as with - the `counteren` CSRs, when a `stateen` CSR prevents access to state by less-privileged levels, an attempt in one of those - privilege modes to execute an instruction that would read or write the protected state raises an illegal instruction - exception, or, if executing in VS or VU mode and the circumstances for a virtual instruction exception apply, raises - a virtual instruction exception instead of an illegal instruction exception. - - When this extension is not implemented, all state added by an extension is accessible as defined by that extension. - - When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute in that privilege mode an - instruction that implicitly updates the state without reading it may or may not raise an illegal instruction or - virtual instruction exception. Such cases must be disambiguated by being explicitly specified one way or the other. - - In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the ISA extensions that - introduce the controlled state. - - For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching - `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an - `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently - inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are - applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, - through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated - from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant - end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher - `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in - the matching `sstateen` CSRs. - - Each standard-defined bit of a `stateen` CSR is WARL and may be read-only zero or one, subject to the following conditions. - - Bits in any `stateen` CSR that are defined to control state that a hart doesn’t implement are read-only zeros for that - hart. Likewise, all reserved bits not yet given a defined meaning are also read-only zeros. For every bit in an `mstateen` - CSR that is zero (whether read-only zero or set to zero), the same bit appears as read-only zero in the matching `hstateen` - and `sstateen` CSRs. For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), the same bit - appears as read-only zero in `sstateen` when accessed in VS-mode. - - A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching - `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. A bit in an `hstateen` CSR cannot be read-only one unless - the same bit is read-only one in the matching `mstateen` CSR. - - On reset, all writable `mstateen` bits are initialized by the hardware to zeros. If machine-level software changes these - values, it is responsible for initializing the corresponding writable bits of the `hstateen` and `sstateen` CSRs to zeros - too. Software at each privilege level should set its respective `stateen` CSRs to indicate the state it is prepared to - allow less-privileged software to access. For OSes and hypervisors, this usually means the state that the OS or hypervisor - is prepared to swap on a context switch, or to manage in some other way. - - For each `mstateen` CSR, bit 63 is defined to control access to the matching `sstateen` and `hstateen` CSRs. That is, bit 63 - of `mstateen0` controls access to `sstateen0` and `hstateen0`; bit 63 of `mstateen1` controls access to `sstateen1` and `hstateen1`; - etc. Likewise, bit 63 of each `hstateen` correspondingly controls access to the matching `sstateen` CSR. - - A hypervisor may need this control over accesses to the `sstateen` CSRs if it ever must emulate for a virtual machine - an extension that is supposed to be affected by a bit in an `sstateen` CSR. Even if such emulation is uncommon, it should not be excluded. - - Machine-level software needs identical control to be able to emulate the hypervisor extension. That is, machine level needs control over - accesses to the supervisor-level `sstateen` CSRs in order to emulate the `hstateen` CSRs, which have such control. - - Bit 63 of each `mstateen` CSR may be read-only zero only if the hypervisor extension is not implemented and the matching - supervisor-level `sstateen` CSR is all read-only zeros. In that case, machine-level software should emulate attempts to access - the affected `sstateen` CSR from S-mode, ignoring writes and returning zero for reads. Bit 63 of each `hstateen` CSR is always - writable (not read-only). +description: + - id: csr-sstateen3-purpose + normative: true + text: | + Each bit of a `stateen` CSR controls less-privileged access to an extension’s state, + for an extension that was not deemed "worthy" of a full XS field in `sstatus` like the + FS and VS fields for the F and V extensions. + - id: csr-sstateen3-num-justification + normative: false + text: | + The number of registers provided at each level is four because it is believed that + 4 * 64 = 256 bits for machine and hypervisor levels, and 4 * 32 = 128 bits for + supervisor level, will be adequate for many years to come, perhaps for as long as + the RISC-V ISA is in use. + The exact number four is an attempted compromise between providing too few bits on + the one hand and going overboard with CSRs that will never be used on the other. + - id: csr-sstateen3-scope + normative: true + text: | + The `stateen` registers at each level control access to state at all less-privileged + levels, but not at its own level. + - id: csr-sstateen3-effect + normative: true + text: | + When a `stateen` CSR prevents access to state for a privilege mode, attempting to execute + in that privilege mode an instruction that implicitly updates the state without reading + it may or may not raise an illegal instruction or virtual instruction exception. + Such cases must be disambiguated by being explicitly specified one way or the other. + In some cases, the bits of the `stateen` CSRs will have a dual purpose as enables for the + ISA extensions that introduce the controlled state. + - id: csr-sstateen3-bit-allocation + normative: true + text: | + For every bit with a defined purpose in an `sstateen` CSR, the same bit is defined in the matching + `mstateen` CSR to control access below machine level to the same state. The upper 32 bits of an + `mstateen` CSR (or for RV32, the corresponding high-half CSR) control access to state that is inherently + inaccessible to user level, so no corresponding enable bits in the supervisor-level `sstateen` CSR are + applicable. The intention is to allocate bits for this purpose starting at the most-significant end, bit 63, + through to bit 32, and then on to the next-higher `mstateen` CSR. If the rate that bits are being allocated + from the least-significant end for `sstateen` CSRs is sufficiently low, allocation from the most-significant + end of `mstateen` CSRs may be allowed to encroach on the lower 32 bits before jumping to the next-higher + `mstateen` CSR. In that case, the bit positions of "encroaching" bits will remain forever read-only zeros in + the matching `sstateen` CSRs. + - id: csr-sstateen3-zero + normative: true + text: | + For every bit in an `mstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in the matching `hstateen` and `sstateen` CSRs. + For every bit in an `hstateen` CSR that is zero (whether read-only zero or set to zero), + the same bit appears as read-only zero in `sstateen` when accessed in VS-mode. + - id: csr-sstateen3-read-only + normative: true + text: | + A bit in a supervisor-level `sstateen` CSR cannot be read-only one unless the same bit is read-only one in the matching + `mstateen` CSR and, if it exists, in the matching `hstateen` CSR. Bit 63 of each `mstateen` CSR may be read-only zero + only if the hypervisor extension is not implemented and the matching supervisor-level `sstateen` CSR is all read-only zeros. definedBy: allOf: From a3f75bba18433063f2f3d443b77c0795d75139d7 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Mon, 5 May 2025 17:40:29 +0000 Subject: [PATCH 12/38] finish adding structured format --- arch/csr/hstateen0h.yaml | 19 +++++++++++-------- arch/csr/hstateen1h.yaml | 19 +++++++++++-------- arch/csr/hstateen2h.yaml | 19 +++++++++++-------- arch/csr/hstateen3h.yaml | 19 +++++++++++-------- arch/csr/mstateen0h.yaml | 14 +++++++++----- arch/csr/mstateen1h.yaml | 14 +++++++++----- arch/csr/mstateen2h.yaml | 14 +++++++++----- arch/csr/mstateen3h.yaml | 14 +++++++++----- 8 files changed, 80 insertions(+), 52 deletions(-) diff --git a/arch/csr/hstateen0h.yaml b/arch/csr/hstateen0h.yaml index eee33014e..4515b2a10 100644 --- a/arch/csr/hstateen0h.yaml +++ b/arch/csr/hstateen0h.yaml @@ -8,15 +8,18 @@ address: 0x61C priv_mode: S length: 32 base: 32 -description: | - For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), - `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at - supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, - another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. +description: + - id: csr-hstateen0h-purpose + normative: true + text: | + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), + `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, + another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. - For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding - set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, - `hstateen1h`, `hstateen2h`, and `hstateen3h`. + For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding + set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, + `hstateen1h`, `hstateen2h`, and `hstateen3h`. definedBy: allOf: diff --git a/arch/csr/hstateen1h.yaml b/arch/csr/hstateen1h.yaml index f321dbb3b..0eb74a952 100644 --- a/arch/csr/hstateen1h.yaml +++ b/arch/csr/hstateen1h.yaml @@ -8,15 +8,18 @@ address: 0x61D priv_mode: S length: 32 base: 32 -description: | - For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), - `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at - supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, - another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. +description: + - id: csr-hstateen0h-purpose + normative: true + text: | + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), + `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, + another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. - For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding - set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, - `hstateen1h`, `hstateen2h`, and `hstateen3h`. + For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding + set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, + `hstateen1h`, `hstateen2h`, and `hstateen3h`. definedBy: allOf: diff --git a/arch/csr/hstateen2h.yaml b/arch/csr/hstateen2h.yaml index f85cb115a..f50339d4f 100644 --- a/arch/csr/hstateen2h.yaml +++ b/arch/csr/hstateen2h.yaml @@ -8,15 +8,18 @@ address: 0x61E priv_mode: S length: 32 base: 32 -description: | - For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), - `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at - supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, - another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. +description: + - id: csr-hstateen0h-purpose + normative: true + text: | + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), + `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, + another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. - For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding - set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, - `hstateen1h`, `hstateen2h`, and `hstateen3h`. + For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding + set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, + `hstateen1h`, `hstateen2h`, and `hstateen3h`. definedBy: allOf: diff --git a/arch/csr/hstateen3h.yaml b/arch/csr/hstateen3h.yaml index 2026259d8..6d311f23c 100644 --- a/arch/csr/hstateen3h.yaml +++ b/arch/csr/hstateen3h.yaml @@ -8,15 +8,18 @@ address: 0x61F priv_mode: S length: 32 base: 32 -description: | - For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), - `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at - supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, - another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. +description: + - id: csr-hstateen0h-purpose + normative: true + text: | + For RV64 harts, the Smstateen/Ssstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State Enable 0), + `mstateen1`, `mstateen2`, and `mstateen3`. If supervisor mode is implemented, another four CSRs are defined at + supervisor level: `sstateen0`, `sstateen1`, `sstateen2`, and `sstateen3`. And if the hypervisor extension is implemented, + another set of CSRs is added: `hstateen0`, `hstateen1`, `hstateen2`, and `hstateen3`. - For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding - set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, - `hstateen1h`, `hstateen2h`, and `hstateen3h`. + For RV32, the registers listed above are 32-bit, and for the machine-level and hypervisor CSRs there is a corresponding + set of high-half CSRs for the upper 32 bits of each register: `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`, `hstateen0h`, + `hstateen1h`, `hstateen2h`, and `hstateen3h`. definedBy: allOf: diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml index 8645f0e2c..7e83f974d 100644 --- a/arch/csr/mstateen0h.yaml +++ b/arch/csr/mstateen0h.yaml @@ -8,11 +8,15 @@ address: 0x31C priv_mode: M length: 32 base: 32 -description: | - For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State - Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the - machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: - `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. +description: + - id: csr-mstateen0h-purpose + normative: true + text: | + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State + Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the + machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: + `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. + definedBy: Smstateen fields: SE0: diff --git a/arch/csr/mstateen1h.yaml b/arch/csr/mstateen1h.yaml index bcba1dc38..0b9373d4e 100644 --- a/arch/csr/mstateen1h.yaml +++ b/arch/csr/mstateen1h.yaml @@ -8,11 +8,15 @@ address: 0x31D priv_mode: M length: 32 base: 32 -description: | - For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State - Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the - machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: - `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. +description: + - id: csr-mstateen1h-purpose + normative: true + text: | + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State + Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the + machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: + `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. + definedBy: Smstateen fields: SE0: diff --git a/arch/csr/mstateen2h.yaml b/arch/csr/mstateen2h.yaml index 5b19e2923..ba419acaa 100644 --- a/arch/csr/mstateen2h.yaml +++ b/arch/csr/mstateen2h.yaml @@ -8,11 +8,15 @@ address: 0x31E priv_mode: M length: 32 base: 32 -description: | - For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State - Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the - machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: - `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. +description: + - id: csr-mstateen2h-purpose + normative: true + text: | + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State + Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the + machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: + `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. + definedBy: Smstateen fields: SE0: diff --git a/arch/csr/mstateen3h.yaml b/arch/csr/mstateen3h.yaml index ed2864555..32e3ee02c 100644 --- a/arch/csr/mstateen3h.yaml +++ b/arch/csr/mstateen3h.yaml @@ -8,11 +8,15 @@ address: 0x31F priv_mode: M length: 32 base: 32 -description: | - For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State - Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the - machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: - `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. +description: + - id: csr-mstateen3h-purpose + normative: true + text: | + For RV64 harts, the Smstateen extension adds four new 64-bit CSRs at machine level: `mstateen0` (Machine State + Enable 0), `mstateen1`, `mstateen2`, and `mstateen3`. For RV32, the registers listed above are 32-bit, and for the + machine-level CSRs there is a corresponding set of high-half CSRs for the upper 32 bits of each register: + `mstateen0h`, `mstateen1h`, `mstateen2h`, `mstateen3h`. + definedBy: Smstateen fields: SE0: From f4c73f3e0cdbe1eab497b07bfa0efec92e6c6fa3 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Mon, 5 May 2025 21:17:42 +0000 Subject: [PATCH 13/38] change mstateen* reset values to 0 --- arch/csr/mstateen0.yaml | 20 ++++++++++---------- arch/csr/mstateen0h.yaml | 14 +++++++------- arch/csr/mstateen1.yaml | 2 +- arch/csr/mstateen1h.yaml | 2 +- arch/csr/mstateen2.yaml | 2 +- arch/csr/mstateen2h.yaml | 2 +- arch/csr/mstateen3.yaml | 2 +- arch/csr/mstateen3h.yaml | 2 +- 8 files changed, 23 insertions(+), 23 deletions(-) diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index 69ab46c02..847003be5 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -72,7 +72,7 @@ fields: description: | The SE0 bit in `mstateen0` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 ENVCFG: long_name: henvcfg, henvcfgh, and senvcfg access control location: 62 @@ -83,7 +83,7 @@ fields: description: | The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 CSRIND: long_name: siselect, sireg*, vsiselect, and vsireg* access control location: 60 @@ -93,7 +93,7 @@ fields: The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 AIA: long_name: Ssaia state access control location: 59 @@ -103,7 +103,7 @@ fields: The AIA bit in `mstateen0` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 IMSIC: long_name: IMSIC state access control location: 58 @@ -113,7 +113,7 @@ fields: The IMSIC bit in `mstateen0` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, provided by the Ssaia extension. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 CONTEXT: long_name: scontext and hcontext access control location: 57 @@ -123,7 +123,7 @@ fields: The CONTEXT bit in `mstateen0` controls access to the `scontext` and `hcontext` CSRs provided by the Sdtrig extension. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 P1P13: long_name: hedelegh access control location: 56 @@ -132,7 +132,7 @@ fields: The P1P13 bit in `mstateen0` controls access to the `hedelegh` introduced by Privileged Specification Version 1.13. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 JVT: long_name: jvt access control location: 2 @@ -140,7 +140,7 @@ fields: description: | The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 FCSR: long_name: fcsr access control location: 1 @@ -156,7 +156,7 @@ fields: instruction trap (or virtual instruction trap, if relevant), as though they all access `fcsr`, regardless of whether they really do. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 C: long_name: custom state access control location: 0 @@ -165,4 +165,4 @@ fields: these registers is not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, `hstateen0`, or `sstateen0`. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml index 7e83f974d..068fa56e7 100644 --- a/arch/csr/mstateen0h.yaml +++ b/arch/csr/mstateen0h.yaml @@ -29,7 +29,7 @@ fields: description: | The SE0 bit in `mstateen0h` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 ENVCFG: long_name: henvcfg, henvcfgh, and senvcfg access control location: 30 @@ -43,7 +43,7 @@ fields: description: | The ENVCFG bit in `mstateen0h` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 CSRIND: long_name: siselect, sireg*, vsiselect, and vsireg* access control location: 28 @@ -56,7 +56,7 @@ fields: The CSRIND bit in `mstateen0h` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 AIA: long_name: Ssaia state access control location: 27 @@ -69,7 +69,7 @@ fields: The AIA bit in `mstateen0h` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 IMSIC: long_name: IMSIC state access control location: 26 @@ -82,7 +82,7 @@ fields: The IMSIC bit in `mstateen0h` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, provided by the Ssaia extension. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 CONTEXT: long_name: scontext and hcontext access control location: 25 @@ -95,7 +95,7 @@ fields: The CONTEXT bit in `mstateen0h` controls access to the `scontext` and `hcontext` CSRs provided by the Sdtrig extension. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 P1P13: long_name: hedelegh access control location: 24 @@ -107,5 +107,5 @@ fields: The P1P13 bit in `mstateen0h` controls access to the `hedelegh` introduced by Privileged Specification Version 1.13. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 sw_read(): return $bits(CSR[mstateen0])[63:32]; diff --git a/arch/csr/mstateen1.yaml b/arch/csr/mstateen1.yaml index 6a727286b..1bd314cab 100644 --- a/arch/csr/mstateen1.yaml +++ b/arch/csr/mstateen1.yaml @@ -72,4 +72,4 @@ fields: description: | The SE0 bit in `mstateen1` controls access to the `hstateen1`, `hstateen1h`, and the `sstateen1` CSRs. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 diff --git a/arch/csr/mstateen1h.yaml b/arch/csr/mstateen1h.yaml index 0b9373d4e..ff0993311 100644 --- a/arch/csr/mstateen1h.yaml +++ b/arch/csr/mstateen1h.yaml @@ -29,5 +29,5 @@ fields: description: | The SE0 bit in `mstateen1h` controls access to the `hstateen1`, `hstateen1h`, and the `sstateen1` CSRs. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 sw_read(): return $bits(CSR[mstateen1])[63:32]; diff --git a/arch/csr/mstateen2.yaml b/arch/csr/mstateen2.yaml index 59140ee2a..d51062bc9 100644 --- a/arch/csr/mstateen2.yaml +++ b/arch/csr/mstateen2.yaml @@ -72,4 +72,4 @@ fields: description: | The SE0 bit in `mstateen2` controls access to the `hstateen2`, `hstateen2h`, and the `sstateen2` CSRs. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 diff --git a/arch/csr/mstateen2h.yaml b/arch/csr/mstateen2h.yaml index ba419acaa..d86a62118 100644 --- a/arch/csr/mstateen2h.yaml +++ b/arch/csr/mstateen2h.yaml @@ -29,5 +29,5 @@ fields: description: | The SE0 bit in `mstateen2h` controls access to the `hstateen2`, `hstateen2h`, and the `sstateen2` CSRs. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 sw_read(): return $bits(CSR[mstateen2])[63:32]; diff --git a/arch/csr/mstateen3.yaml b/arch/csr/mstateen3.yaml index 608ff6eea..78f808417 100644 --- a/arch/csr/mstateen3.yaml +++ b/arch/csr/mstateen3.yaml @@ -72,4 +72,4 @@ fields: description: | The SE0 bit in `mstateen3` controls access to the `hstateen3`, `hstateen3h`, and the `sstateen3` CSRs. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 diff --git a/arch/csr/mstateen3h.yaml b/arch/csr/mstateen3h.yaml index 32e3ee02c..6e46bd2aa 100644 --- a/arch/csr/mstateen3h.yaml +++ b/arch/csr/mstateen3h.yaml @@ -29,5 +29,5 @@ fields: description: | The SE0 bit in `mstateen3h` controls access to the `hstateen3`, `hstateen3h`, and the `sstateen3` CSRs. type: RW - reset_value: UNDEFINED_LEGAL + reset_value: 0 sw_read(): return $bits(CSR[mstateen3])[63:32]; From de434ae20348e3f86cc2ea112cd7add89ff241da Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Tue, 6 May 2025 15:48:28 +0000 Subject: [PATCH 14/38] docs(stateen): comment out Zfinx & Zdinx code + add sw_read --- arch/csr/hstateen0.yaml | 11 +++++++++-- arch/csr/hstateen1.yaml | 7 +++++++ arch/csr/hstateen2.yaml | 7 +++++++ arch/csr/hstateen3.yaml | 7 +++++++ arch/csr/mstateen0.yaml | 4 ++-- arch/csr/sstateen0.yaml | 18 ++++++++++++++++-- arch/csr/sstateen1.yaml | 14 ++++++++++++++ arch/csr/sstateen2.yaml | 14 ++++++++++++++ arch/csr/sstateen3.yaml | 14 ++++++++++++++ 9 files changed, 90 insertions(+), 6 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 8b3121a04..0b45c0174 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -134,8 +134,8 @@ fields: FCSR: long_name: fcsr access control location: 1 - definedBy: - anyOf: [Zfinx, Zdinx] + #definedBy: + #anyOf: [Zfinx, Zdinx] description: | The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related @@ -156,3 +156,10 @@ fields: standard CSR, either `mstateen0`, `hstateen0`, or `sstateen0`. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): | + # for every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching hstateen CSR + + Bit<64> mstateen0_mask = CSR[mstateen0].csr_value; + Bit<64> hstateen0_value = csr_value & mstateen0_mask; + return hstateen0_value; diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index 40294535d..d42221696 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -67,3 +67,10 @@ fields: The SE0 bit in `hstateen1` controls access to the `sstateen1` CSR. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): | + # for every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching hstateen CSR + + Bit<64> mstateen1_mask = CSR[mstateen1].csr_value; + Bit<64> hstateen1_value = csr_value & mstateen1_mask; + return hstateen1_value; diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index f43616a7e..7345ab91e 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -67,3 +67,10 @@ fields: The SE0 bit in `hstateen2` controls access to the `sstateen2` CSR. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): | + # for every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching hstateen CSR + + Bit<64> mstateen2_mask = CSR[mstateen2].csr_value; + Bit<64> hstateen2_value = csr_value & mstateen2_mask; + return hstateen2_value; diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index f53609100..140555ed8 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -67,3 +67,10 @@ fields: The SE0 bit in `hstateen3` controls access to the `sstateen3` CSR. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): | + # for every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching hstateen CSR + + Bit<64> mstateen3_mask = CSR[mstateen3].csr_value; + Bit<64> hstateen3_value = csr_value & mstateen3_mask; + return hstateen3_value; diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index 847003be5..664dc9fc4 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -144,8 +144,8 @@ fields: FCSR: long_name: fcsr access control location: 1 - definedBy: - anyOf: [Zfinx, Zdinx] + #definedBy: + #anyOf: [Zfinx, Zdinx] description: | The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index 5fbd14c04..463f7789f 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -80,8 +80,8 @@ fields: FCSR: long_name: fcsr access control location: 1 - definedBy: - anyOf: [Zfinx, Zdinx] + #definedBy: + #anyOf: [Zfinx, Zdinx] description: | The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related @@ -102,3 +102,17 @@ fields: `hstateen0`, or `sstateen0`. type: RW reset_value: UNDEFINED_LEGAL +sw_read(): | + # For every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching sstateen CSR. + Bit<64> mstateen0_mask = CSR[mstateen0].csr_value; + Bit<64> sstateen0_value = csr_value & mstateen0_mask; + + # For every bit in an hstateen CSR that is zero, the same bit + # appears as read-only zero in sstateen when accessed in VS-mode. + if (mode() == PrivilegeMode::VS) { + Bit<64> hstateen0_mask = CSR[hstateen0].csr_value; + sstateen0_value = sstateen0_value & hstateen0_mask; + } + + return sstateen0_value; diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index d189230b2..846c77953 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -76,3 +76,17 @@ fields: description: Data value type: RW reset_value: UNDEFINED_LEGAL +sw_read(): | + # For every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching sstateen CSR. + Bit<64> mstateen1_mask = CSR[mstateen1].csr_value; + Bit<64> sstateen1_value = csr_value & mstateen1_mask; + + # For every bit in an hstateen CSR that is zero, the same bit + # appears as read-only zero in sstateen when accessed in VS-mode. + if (mode() == PrivilegeMode::VS) { + Bit<64> hstateen1_mask = CSR[hstateen1].csr_value; + sstateen1_value = sstateen1_value & hstateen1_mask; + } + + return sstateen1_value; diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index 8a251bb1d..33237d2f7 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -76,3 +76,17 @@ fields: description: Data value type: RW reset_value: UNDEFINED_LEGAL +sw_read(): | + # For every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching sstateen CSR. + Bit<64> mstateen2_mask = CSR[mstateen2].csr_value; + Bit<64> sstateen2_value = csr_value & mstateen2_mask; + + # For every bit in an hstateen CSR that is zero, the same bit + # appears as read-only zero in sstateen when accessed in VS-mode. + if (mode() == PrivilegeMode::VS) { + Bit<64> hstateen2_mask = CSR[hstateen2].csr_value; + sstateen2_value = sstateen2_value & hstateen2_mask; + } + + return sstateen2_value; diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index d8a76689c..16914a786 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -76,3 +76,17 @@ fields: description: Data value type: RW reset_value: UNDEFINED_LEGAL +sw_read(): | + # For every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching sstateen CSR. + Bit<64> mstateen3_mask = CSR[mstateen3].csr_value; + Bit<64> sstateen3_value = csr_value & mstateen3_mask; + + # For every bit in an hstateen CSR that is zero, the same bit + # appears as read-only zero in sstateen when accessed in VS-mode. + if (mode() == PrivilegeMode::VS) { + Bit<64> hstateen3_mask = CSR[hstateen3].csr_value; + sstateen3_value = sstateen3_value & hstateen3_mask; + } + + return sstateen3_value; From d074a3e8acd0ce0fb6980cddb40b211bee01aef1 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Tue, 6 May 2025 15:52:00 +0000 Subject: [PATCH 15/38] docs(stateen): change C field description --- arch/csr/hstateen0.yaml | 6 +++--- arch/csr/mstateen0.yaml | 4 ++-- arch/csr/sstateen0.yaml | 4 ++-- 3 files changed, 7 insertions(+), 7 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 0b45c0174..3e76d5054 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -151,9 +151,9 @@ fields: long_name: custom state access control location: 0 description: | - The C bit controls access to any and all custom state. This bit is not custom state itself. - The C bit of these registers is not custom state itself; it is a standard field of a - standard CSR, either `mstateen0`, `hstateen0`, or `sstateen0`. + The C bit controls access to any and all custom state. The C bit of these registers is + not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, + `hstateen0`, or `sstateen0`. type: RW reset_value: UNDEFINED_LEGAL sw_read(): | diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index 664dc9fc4..ab449eb20 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -161,8 +161,8 @@ fields: long_name: custom state access control location: 0 description: | - The C bit controls access to any and all custom state. This bit is not custom state itself. The C bit of - these registers is not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, + The C bit controls access to any and all custom state. The C bit of these registers is + not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, `hstateen0`, or `sstateen0`. type: RW reset_value: 0 diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index 463f7789f..c7435e2d7 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -97,8 +97,8 @@ fields: long_name: custom state access control location: 0 description: | - The C bit controls access to any and all custom state. This bit is not custom state itself. The C bit of - these registers is not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, + The C bit controls access to any and all custom state. The C bit of these registers is + not custom state itself; it is a standard field of a standard CSR, either `mstateen0`, `hstateen0`, or `sstateen0`. type: RW reset_value: UNDEFINED_LEGAL From efc3bffd6de1bcd75aade8d78d990c9b64e18adb Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Tue, 6 May 2025 16:04:40 +0000 Subject: [PATCH 16/38] docs(stateen): fix syntax errors --- arch/csr/hstateen0.yaml | 4 ++-- arch/csr/sstateen0.yaml | 6 +++--- arch/csr/sstateen1.yaml | 4 ++-- arch/csr/sstateen2.yaml | 6 +++--- arch/csr/sstateen3.yaml | 6 +++--- 5 files changed, 13 insertions(+), 13 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 3e76d5054..f483fe46b 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -160,6 +160,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bit<64> mstateen0_mask = CSR[mstateen0].csr_value; - Bit<64> hstateen0_value = csr_value & mstateen0_mask; + Bits<64> mstateen0_mask = CSR[mstateen0].csr_value; + Bits<64> hstateen0_value = csr_value & mstateen0_mask; return hstateen0_value; diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index c7435e2d7..7641b1ad1 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -105,13 +105,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bit<64> mstateen0_mask = CSR[mstateen0].csr_value; - Bit<64> sstateen0_value = csr_value & mstateen0_mask; + Bits<64> mstateen0_mask = CSR[mstateen0].csr_value; + Bits<64> sstateen0_value = csr_value & mstateen0_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bit<64> hstateen0_mask = CSR[hstateen0].csr_value; + Bits<64> hstateen0_mask = CSR[hstateen0].csr_value; sstateen0_value = sstateen0_value & hstateen0_mask; } diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index 846c77953..411126fb4 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -79,8 +79,8 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bit<64> mstateen1_mask = CSR[mstateen1].csr_value; - Bit<64> sstateen1_value = csr_value & mstateen1_mask; + Bits<64> mstateen1_mask = CSR[mstateen1].csr_value; + Bits<64> sstateen1_value = csr_value & mstateen1_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index 33237d2f7..0c8137405 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -79,13 +79,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bit<64> mstateen2_mask = CSR[mstateen2].csr_value; - Bit<64> sstateen2_value = csr_value & mstateen2_mask; + Bits<64> mstateen2_mask = CSR[mstateen2].csr_value; + Bits<64> sstateen2_value = csr_value & mstateen2_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bit<64> hstateen2_mask = CSR[hstateen2].csr_value; + Bits<64> hstateen2_mask = CSR[hstateen2].csr_value; sstateen2_value = sstateen2_value & hstateen2_mask; } diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index 16914a786..637f2628c 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -79,13 +79,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bit<64> mstateen3_mask = CSR[mstateen3].csr_value; - Bit<64> sstateen3_value = csr_value & mstateen3_mask; + Bits<64> mstateen3_mask = CSR[mstateen3].csr_value; + Bits<64> sstateen3_value = csr_value & mstateen3_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bit<64> hstateen3_mask = CSR[hstateen3].csr_value; + Bits<64> hstateen3_mask = CSR[hstateen3].csr_value; sstateen3_value = sstateen3_value & hstateen3_mask; } From 659aa3a8e7113b3576168ccbc03677f87e2e3ed6 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Tue, 6 May 2025 16:27:25 +0000 Subject: [PATCH 17/38] docs(stateen): syntax --- arch/csr/hstateen0.yaml | 2 +- arch/csr/hstateen1.yaml | 4 ++-- arch/csr/hstateen2.yaml | 4 ++-- arch/csr/hstateen3.yaml | 4 ++-- arch/csr/sstateen0.yaml | 4 ++-- arch/csr/sstateen1.yaml | 4 ++-- arch/csr/sstateen2.yaml | 4 ++-- arch/csr/sstateen3.yaml | 4 ++-- 8 files changed, 15 insertions(+), 15 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index f483fe46b..efa4345cc 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -160,6 +160,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bits<64> mstateen0_mask = CSR[mstateen0].csr_value; + Bits<64> mstateen0_mask = CSR[mstateen0]; Bits<64> hstateen0_value = csr_value & mstateen0_mask; return hstateen0_value; diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index d42221696..58df58fdd 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -71,6 +71,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bit<64> mstateen1_mask = CSR[mstateen1].csr_value; - Bit<64> hstateen1_value = csr_value & mstateen1_mask; + Bits<64> mstateen1_mask = CSR[mstateen1]; + Bits<64> hstateen1_value = csr_value & mstateen1_mask; return hstateen1_value; diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index 7345ab91e..e41270bb3 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -71,6 +71,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bit<64> mstateen2_mask = CSR[mstateen2].csr_value; - Bit<64> hstateen2_value = csr_value & mstateen2_mask; + Bits<64> mstateen2_mask = CSR[mstateen2]; + Bits<64> hstateen2_value = csr_value & mstateen2_mask; return hstateen2_value; diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index 140555ed8..9ce4f6274 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -71,6 +71,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bit<64> mstateen3_mask = CSR[mstateen3].csr_value; - Bit<64> hstateen3_value = csr_value & mstateen3_mask; + Bits<64> mstateen3_mask = CSR[mstateen3]; + Bits<64> hstateen3_value = csr_value & mstateen3_mask; return hstateen3_value; diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index 7641b1ad1..f6f63bd61 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -105,13 +105,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen0_mask = CSR[mstateen0].csr_value; + Bits<64> mstateen0_mask = CSR[mstateen0]; Bits<64> sstateen0_value = csr_value & mstateen0_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen0_mask = CSR[hstateen0].csr_value; + Bits<64> hstateen0_mask = CSR[hstateen0]; sstateen0_value = sstateen0_value & hstateen0_mask; } diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index 411126fb4..bd650f0ce 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -79,13 +79,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen1_mask = CSR[mstateen1].csr_value; + Bits<64> mstateen1_mask = CSR[mstateen1]; Bits<64> sstateen1_value = csr_value & mstateen1_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bit<64> hstateen1_mask = CSR[hstateen1].csr_value; + Bit<64> hstateen1_mask = CSR[hstateen1]; sstateen1_value = sstateen1_value & hstateen1_mask; } diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index 0c8137405..1b9a12fd7 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -79,13 +79,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen2_mask = CSR[mstateen2].csr_value; + Bits<64> mstateen2_mask = CSR[mstateen2]; Bits<64> sstateen2_value = csr_value & mstateen2_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen2_mask = CSR[hstateen2].csr_value; + Bits<64> hstateen2_mask = CSR[hstateen2]; sstateen2_value = sstateen2_value & hstateen2_mask; } diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index 637f2628c..b616d1900 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -79,13 +79,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen3_mask = CSR[mstateen3].csr_value; + Bits<64> mstateen3_mask = CSR[mstateen3]; Bits<64> sstateen3_value = csr_value & mstateen3_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen3_mask = CSR[hstateen3].csr_value; + Bits<64> hstateen3_mask = CSR[hstateen3]; sstateen3_value = sstateen3_value & hstateen3_mask; } From 405103b5e10aa012d7466a8cc794bd8b43d1ebd2 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 8 May 2025 17:22:09 +0000 Subject: [PATCH 18/38] docs(stateen): add sw_write for sstateen CSRs --- arch/csr/hstateen0.yaml | 2 +- arch/csr/hstateen1.yaml | 2 +- arch/csr/hstateen2.yaml | 2 +- arch/csr/hstateen3.yaml | 2 +- arch/csr/sstateen0.yaml | 25 +++++++++++++++++++++++-- arch/csr/sstateen1.yaml | 18 ++++++++++++++++-- arch/csr/sstateen2.yaml | 18 ++++++++++++++++-- arch/csr/sstateen3.yaml | 18 ++++++++++++++++-- 8 files changed, 75 insertions(+), 12 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index efa4345cc..f483fe46b 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -160,6 +160,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bits<64> mstateen0_mask = CSR[mstateen0]; + Bits<64> mstateen0_mask = CSR[mstateen0].csr_value; Bits<64> hstateen0_value = csr_value & mstateen0_mask; return hstateen0_value; diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index 58df58fdd..50252088a 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -71,6 +71,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bits<64> mstateen1_mask = CSR[mstateen1]; + Bits<64> mstateen1_mask = CSR[mstateen1].csr_value; Bits<64> hstateen1_value = csr_value & mstateen1_mask; return hstateen1_value; diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index e41270bb3..7fdeda548 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -71,6 +71,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bits<64> mstateen2_mask = CSR[mstateen2]; + Bits<64> mstateen2_mask = CSR[mstateen2].csr_value; Bits<64> hstateen2_value = csr_value & mstateen2_mask; return hstateen2_value; diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index 9ce4f6274..c8a81ca64 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -71,6 +71,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bits<64> mstateen3_mask = CSR[mstateen3]; + Bits<64> mstateen3_mask = CSR[mstateen3].csr_value; Bits<64> hstateen3_value = csr_value & mstateen3_mask; return hstateen3_value; diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index f6f63bd61..7346331ea 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -77,6 +77,13 @@ fields: The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].JVT == 1'b0){ + return 0; + } + else if (mode() == PrivilegeMode::VS && CSR[hstateen0].JVT == 1'b0) { + return 0; + } FCSR: long_name: fcsr access control location: 1 @@ -93,6 +100,13 @@ fields: `fcsr`, regardless of whether they really do. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].FCSR == 1'b0){ + return 0; + } + else if (mode() == PrivilegeMode::VS && CSR[hstateen0].FCSR == 1'b0) { + return 0; + } C: long_name: custom state access control location: 0 @@ -102,16 +116,23 @@ fields: `hstateen0`, or `sstateen0`. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].C == 1'b0){ + return 0; + } + else if (mode() == PrivilegeMode::VS && CSR[hstateen0].C == 1'b0) { + return 0; + } sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen0_mask = CSR[mstateen0]; + Bits<64> mstateen0_mask = CSR[mstateen0].csr_value; Bits<64> sstateen0_value = csr_value & mstateen0_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen0_mask = CSR[hstateen0]; + Bits<64> hstateen0_mask = CSR[hstateen0].csr_value; sstateen0_value = sstateen0_value & hstateen0_mask; } diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index bd650f0ce..8d7c0b189 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -75,17 +75,31 @@ fields: location_rv32: 31-0 description: Data value type: RW + sw_write(csr_value): | + # For every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching sstateen CSR. + Bits<64> mstateen1_mask = CSR[mstateen1].csr_value; + Bits<64> data_value = csr_value.DATA & mstateen1_mask; + + # For every bit in an hstateen CSR that is zero, the same bit + # appears as read-only zero in sstateen when accessed in VS-mode. + if (mode() == PrivilegeMode::VS) { + Bits<64> hstateen1_mask = CSR[hstateen1].csr_value; + data_value = data_value & hstateen1_mask; + } + + return data_value reset_value: UNDEFINED_LEGAL sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen1_mask = CSR[mstateen1]; + Bits<64> mstateen1_mask = CSR[mstateen1].csr_value; Bits<64> sstateen1_value = csr_value & mstateen1_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bit<64> hstateen1_mask = CSR[hstateen1]; + Bits<64> hstateen1_mask = CSR[hstateen1].csr_value; sstateen1_value = sstateen1_value & hstateen1_mask; } diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index 1b9a12fd7..0c7f5577a 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -75,17 +75,31 @@ fields: location_rv32: 31-0 description: Data value type: RW + sw_write(csr_value): | + # For every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching sstateen CSR. + Bits<64> mstateen2_mask = CSR[mstateen2].csr_value; + Bits<64> data_value = csr_value.DATA & mstateen2_mask; + + # For every bit in an hstateen CSR that is zero, the same bit + # appears as read-only zero in sstateen when accessed in VS-mode. + if (mode() == PrivilegeMode::VS) { + Bits<64> hstateen2_mask = CSR[hstateen2].csr_value; + data_value = data_value & hstateen2_mask; + } + + return data_value; reset_value: UNDEFINED_LEGAL sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen2_mask = CSR[mstateen2]; + Bits<64> mstateen2_mask = CSR[mstateen2].csr_value; Bits<64> sstateen2_value = csr_value & mstateen2_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen2_mask = CSR[hstateen2]; + Bits<64> hstateen2_mask = CSR[hstateen2].csr_value; sstateen2_value = sstateen2_value & hstateen2_mask; } diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index b616d1900..0bf861910 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -75,17 +75,31 @@ fields: location_rv32: 31-0 description: Data value type: RW + sw_write(csr_value): | + # For every bit in an mstateen CSR that is zero, the same bit + # appears as read-only zero in the matching sstateen CSR. + Bits<64> mstateen1_mask = CSR[mstateen1].csr_value; + Bits<64> data_value = csr_value.DATA & mstateen1_mask; + + # For every bit in an hstateen CSR that is zero, the same bit + # appears as read-only zero in sstateen when accessed in VS-mode. + if (mode() == PrivilegeMode::VS) { + Bits<64> hstateen1_mask = CSR[hstateen1].csr_value; + data_value = data_value & hstateen1_mask; + } + + return data_value reset_value: UNDEFINED_LEGAL sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen3_mask = CSR[mstateen3]; + Bits<64> mstateen3_mask = CSR[mstateen3].csr_value; Bits<64> sstateen3_value = csr_value & mstateen3_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen3_mask = CSR[hstateen3]; + Bits<64> hstateen3_mask = CSR[hstateen3].csr_value; sstateen3_value = sstateen3_value & hstateen3_mask; } From 240b8958d0bd5f0495baad1c6d4e105892670e74 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 8 May 2025 17:33:20 +0000 Subject: [PATCH 19/38] docs(stateen): add sw_write for hstateen* CSRs --- arch/csr/hstateen0.yaml | 36 +++++++++++++++++++++++++++ arch/csr/hstateen0h.yaml | 54 +++++++++++++++++++++++++++++++--------- arch/csr/hstateen1.yaml | 4 +++ arch/csr/hstateen1h.yaml | 9 +++++-- arch/csr/hstateen2.yaml | 4 +++ arch/csr/hstateen2h.yaml | 9 +++++-- arch/csr/hstateen3.yaml | 4 +++ arch/csr/hstateen3h.yaml | 9 +++++-- 8 files changed, 111 insertions(+), 18 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index f483fe46b..ba2c7cce5 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -67,6 +67,10 @@ fields: The SE0 bit in `hstateen0` controls access to the `sstateen0` CSR. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].SE0 == 1'b0){ + return 0; + } ENVCFG: long_name: senvcfg access control location: 62 @@ -78,6 +82,10 @@ fields: The ENVCFG bit in `hstateen0` controls access to the `senvcfg` CSRs. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].ENVCFG == 1'b0){ + return 0; + } CSRIND: long_name: siselect and sireg* access control location: 60 @@ -89,6 +97,10 @@ fields: extensions. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].CSRIND == 1'b0){ + return 0; + } AIA: long_name: Ssaia state access control location: 59 @@ -100,6 +112,10 @@ fields: IMSIC bits of `hstateen0`. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].AIA == 1'b0){ + return 0; + } IMSIC: long_name: IMSIC state access control location: 58 @@ -113,6 +129,10 @@ fields: from accessing the hart’s IMSIC the same as setting `hstatus.`VGEIN = 0. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].IMSIC == 1'b0){ + return 0; + } CONTEXT: long_name: scontext access control location: 57 @@ -123,6 +143,10 @@ fields: by the Sdtrig extension. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].CONTEXT == 1'b0){ + return 0; + } JVT: long_name: jvt access control location: 2 @@ -131,6 +155,10 @@ fields: The JVT bit controls access to the `jvt` CSR provided by the Zcmt extension. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].JVT == 1'b0){ + return 0; + } FCSR: long_name: fcsr access control location: 1 @@ -147,6 +175,10 @@ fields: `fcsr`, regardless of whether they really do. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].FCSR == 1'b0){ + return 0; + } C: long_name: custom state access control location: 0 @@ -156,6 +188,10 @@ fields: `hstateen0`, or `sstateen0`. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen0].C == 1'b0){ + return 0; + } sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR diff --git a/arch/csr/hstateen0h.yaml b/arch/csr/hstateen0h.yaml index 4515b2a10..adf489c52 100644 --- a/arch/csr/hstateen0h.yaml +++ b/arch/csr/hstateen0h.yaml @@ -32,8 +32,13 @@ fields: location: 31 alias: hstateen0.SE0 sw_write(csr_value): | - CSR[hstateen0].SE0 = csr_value.SE0; - return csr_value.SE0; + if (CSR[mstateen0].SE0 == 1'b0){ + return 0; + } + else{ + CSR[hstateen0].SE0 = csr_value.SE0; + return csr_value.SE0; + } description: | The SE0 bit in `hstateen0h` controls access to the `sstateen0` CSR. type: RW @@ -46,8 +51,13 @@ fields: version: ">= 1.11" alias: hstateen0.ENVCFG sw_write(csr_value): | - CSR[hstateen0].ENVCFG = csr_value.ENVCFG; - return csr_value.ENVCFG; + if (CSR[mstateen0].ENVCFG == 1'b0){ + return 0; + } + else{ + CSR[hstateen0].ENVCFG = csr_value.ENVCFG; + return csr_value.ENVCFG; + } description: | The ENVCFG bit in `hstateen0h` controls access to the `senvcfg` CSRs. type: RW @@ -58,8 +68,13 @@ fields: definedBy: Sscsrind alias: hstateen0.CSRIND sw_write(csr_value): | - CSR[hstateen0].CSRIND = csr_value.CSRIND; - return csr_value.CSRIND; + if (CSR[mstateen0].CSRIND == 1'b0){ + return 0; + } + else{ + CSR[hstateen0].CSRIND = csr_value.CSRIND; + return csr_value.CSRIND; + } description: | The CSRIND bit in `hstateen0h` controls access to the `siselect` and the `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind @@ -72,8 +87,13 @@ fields: definedBy: Ssaia alias: hstateen0.AIA sw_write(csr_value): | - CSR[hstateen0].AIA = csr_value.AIA; - return csr_value.AIA; + if (CSR[mstateen0].AIA == 1'b0){ + return 0; + } + else{ + CSR[hstateen0].AIA = csr_value.AIA; + return csr_value.AIA; + } description: | The AIA bit in `hstateen0h` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the @@ -86,8 +106,13 @@ fields: definedBy: Ssaia alias: hstateen0.IMSIC sw_write(csr_value): | - CSR[hstateen0].IMSIC = csr_value.IMSIC; - return csr_value.IMSIC; + if (CSR[mstateen0].IMSIC == 1'b0){ + return 0; + } + else{ + CSR[hstateen0].IMSIC = csr_value.IMSIC; + return csr_value.IMSIC; + } description: | The IMSIC bit in `hstateen0h` controls access to the guest IMSIC state, including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension. @@ -102,8 +127,13 @@ fields: definedBy: Sdtrig alias: hstateen0.CONTEXT sw_write(csr_value): | - CSR[hstateen0].CONTEXT = csr_value.CONTEXT; - return csr_value.CONTEXT; + if (CSR[mstateen0].CONTEXT == 1'b0){ + return 0; + } + else{ + CSR[hstateen0].CONTEXT = csr_value.CONTEXT; + return csr_value.CONTEXT; + } description: | The CONTEXT bit in `hstateen0h` controls access to the `scontext` CSR provided by the Sdtrig extension. diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index 50252088a..c2db8bb25 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -67,6 +67,10 @@ fields: The SE0 bit in `hstateen1` controls access to the `sstateen1` CSR. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen1].SE0 == 1'b0){ + return 0; + } sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR diff --git a/arch/csr/hstateen1h.yaml b/arch/csr/hstateen1h.yaml index 0eb74a952..35874cb49 100644 --- a/arch/csr/hstateen1h.yaml +++ b/arch/csr/hstateen1h.yaml @@ -32,8 +32,13 @@ fields: location: 31 alias: hstateen1.SE0 sw_write(csr_value): | - CSR[hstateen1].SE0 = csr_value.SE0; - return csr_value.SE0; + if (CSR[mstateen1].SE0 == 1'b0){ + return 0; + } + else{ + CSR[hstateen1].SE0 = csr_value.SE0; + return csr_value.SE0; + } description: | The SE0 bit in `hstateen1h` controls access to the `sstateen1` CSR. type: RW diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index 7fdeda548..6632c225a 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -67,6 +67,10 @@ fields: The SE0 bit in `hstateen2` controls access to the `sstateen2` CSR. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen2].SE0 == 1'b0){ + return 0; + } sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR diff --git a/arch/csr/hstateen2h.yaml b/arch/csr/hstateen2h.yaml index f50339d4f..b3180b80f 100644 --- a/arch/csr/hstateen2h.yaml +++ b/arch/csr/hstateen2h.yaml @@ -32,8 +32,13 @@ fields: location: 31 alias: hstateen2.SE0 sw_write(csr_value): | - CSR[hstateen2].SE0 = csr_value.SE0; - return csr_value.SE0; + if (CSR[mstateen2].SE0 == 1'b0){ + return 0; + } + else{ + CSR[hstateen2].SE0 = csr_value.SE0; + return csr_value.SE0; + } description: | The SE0 bit in `hstateen2h` controls access to the `sstateen2` CSR. type: RW diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index c8a81ca64..5479e4a6d 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -67,6 +67,10 @@ fields: The SE0 bit in `hstateen3` controls access to the `sstateen3` CSR. type: RW reset_value: UNDEFINED_LEGAL + sw_write(csr_value): | + if (CSR[mstateen3].SE0 == 1'b0){ + return 0; + } sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR diff --git a/arch/csr/hstateen3h.yaml b/arch/csr/hstateen3h.yaml index 6d311f23c..4ba7c95ba 100644 --- a/arch/csr/hstateen3h.yaml +++ b/arch/csr/hstateen3h.yaml @@ -32,8 +32,13 @@ fields: location: 31 alias: hstateen3.SE0 sw_write(csr_value): | - CSR[hstateen3].SE0 = csr_value.SE0; - return csr_value.SE0; + if (CSR[mstateen3].SE0 == 1'b0){ + return 0; + } + else{ + CSR[hstateen3].SE0 = csr_value.SE0; + return csr_value.SE0; + } description: | The SE0 bit in `hstateen3h` controls access to the `sstateen3` CSR. type: RW From 838355d917cd4d569d653dc9d091f7415a3684b2 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 8 May 2025 18:19:15 +0000 Subject: [PATCH 20/38] docs(stateen): syntax fixes --- arch/csr/hstateen0.yaml | 2 +- arch/csr/hstateen1.yaml | 2 +- arch/csr/hstateen2.yaml | 2 +- arch/csr/hstateen3.yaml | 2 +- arch/csr/sstateen0.yaml | 4 ++-- arch/csr/sstateen1.yaml | 8 ++++---- arch/csr/sstateen2.yaml | 8 ++++---- arch/csr/sstateen3.yaml | 12 ++++++------ 8 files changed, 20 insertions(+), 20 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index ba2c7cce5..d4822ad97 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -196,6 +196,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bits<64> mstateen0_mask = CSR[mstateen0].csr_value; + Bits<64> mstateen0_mask = $bits(CSR[mstateen0]); Bits<64> hstateen0_value = csr_value & mstateen0_mask; return hstateen0_value; diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index c2db8bb25..f2e209a01 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -75,6 +75,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bits<64> mstateen1_mask = CSR[mstateen1].csr_value; + Bits<64> mstateen1_mask = $bits(CSR[mstateen1]); Bits<64> hstateen1_value = csr_value & mstateen1_mask; return hstateen1_value; diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index 6632c225a..bcbf972c4 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -75,6 +75,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bits<64> mstateen2_mask = CSR[mstateen2].csr_value; + Bits<64> mstateen2_mask = $bits(CSR[mstateen2]); Bits<64> hstateen2_value = csr_value & mstateen2_mask; return hstateen2_value; diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index 5479e4a6d..b85c9d666 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -75,6 +75,6 @@ sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR - Bits<64> mstateen3_mask = CSR[mstateen3].csr_value; + Bits<64> mstateen3_mask = $bits(CSR[mstateen3]); Bits<64> hstateen3_value = csr_value & mstateen3_mask; return hstateen3_value; diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index 7346331ea..7611f2053 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -126,13 +126,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen0_mask = CSR[mstateen0].csr_value; + Bits<64> mstateen0_mask = $bits(CSR[mstateen0]); Bits<64> sstateen0_value = csr_value & mstateen0_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen0_mask = CSR[hstateen0].csr_value; + Bits<64> hstateen0_mask = $bits(CSR[hstateen0]); sstateen0_value = sstateen0_value & hstateen0_mask; } diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index 8d7c0b189..d35c5e8c3 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -78,13 +78,13 @@ fields: sw_write(csr_value): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen1_mask = CSR[mstateen1].csr_value; + Bits<64> mstateen1_mask = $bits(CSR[mstateen1]); Bits<64> data_value = csr_value.DATA & mstateen1_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen1_mask = CSR[hstateen1].csr_value; + Bits<64> hstateen1_mask = $bits(CSR[hstateen1]); data_value = data_value & hstateen1_mask; } @@ -93,13 +93,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen1_mask = CSR[mstateen1].csr_value; + Bits<64> mstateen1_mask = $bits(CSR[mstateen1]); Bits<64> sstateen1_value = csr_value & mstateen1_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen1_mask = CSR[hstateen1].csr_value; + Bits<64> hstateen1_mask = $bits(CSR[hstateen1]); sstateen1_value = sstateen1_value & hstateen1_mask; } diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index 0c7f5577a..fa5b8e742 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -78,13 +78,13 @@ fields: sw_write(csr_value): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen2_mask = CSR[mstateen2].csr_value; + Bits<64> mstateen2_mask = $bits(CSR[mstateen2]); Bits<64> data_value = csr_value.DATA & mstateen2_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen2_mask = CSR[hstateen2].csr_value; + Bits<64> hstateen2_mask = $bits(CSR[hstateen2]); data_value = data_value & hstateen2_mask; } @@ -93,13 +93,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen2_mask = CSR[mstateen2].csr_value; + Bits<64> mstateen2_mask = $bits(CSR[mstateen2]); Bits<64> sstateen2_value = csr_value & mstateen2_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen2_mask = CSR[hstateen2].csr_value; + Bits<64> hstateen2_mask = $bits(CSR[hstateen2]); sstateen2_value = sstateen2_value & hstateen2_mask; } diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index 0bf861910..845e69a7f 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -78,14 +78,14 @@ fields: sw_write(csr_value): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen1_mask = CSR[mstateen1].csr_value; - Bits<64> data_value = csr_value.DATA & mstateen1_mask; + Bits<64> mstateen3_mask = $bits(CSR[mstateen3]); + Bits<64> data_value = csr_value.DATA & mstateen3_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen1_mask = CSR[hstateen1].csr_value; - data_value = data_value & hstateen1_mask; + Bits<64> hstateen3mask = $bits(CSR[hstateen3]); + data_value = data_value & hstateen3_mask; } return data_value @@ -93,13 +93,13 @@ fields: sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. - Bits<64> mstateen3_mask = CSR[mstateen3].csr_value; + Bits<64> mstateen3_mask = $bits(CSR[mstateen3]); Bits<64> sstateen3_value = csr_value & mstateen3_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen3_mask = CSR[hstateen3].csr_value; + Bits<64> hstateen3_mask = $bits(CSR[hstateen3]); sstateen3_value = sstateen3_value & hstateen3_mask; } From eb9b0034e461f617e2f6aa02758030eb0a1bd903 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 8 May 2025 18:30:03 +0000 Subject: [PATCH 21/38] docs(stateen): syntax fixes --- arch/csr/hstateen0.yaml | 2 +- arch/csr/hstateen1.yaml | 2 +- arch/csr/hstateen2.yaml | 2 +- arch/csr/hstateen3.yaml | 2 +- arch/csr/sstateen0.yaml | 2 +- arch/csr/sstateen1.yaml | 2 +- arch/csr/sstateen2.yaml | 2 +- arch/csr/sstateen3.yaml | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index d4822ad97..662688faa 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -197,5 +197,5 @@ sw_read(): | # appears as read-only zero in the matching hstateen CSR Bits<64> mstateen0_mask = $bits(CSR[mstateen0]); - Bits<64> hstateen0_value = csr_value & mstateen0_mask; + Bits<64> hstateen0_value = $bits(CSR[hstateen0]) & mstateen0_mask; return hstateen0_value; diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index f2e209a01..43b3e19ba 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -76,5 +76,5 @@ sw_read(): | # appears as read-only zero in the matching hstateen CSR Bits<64> mstateen1_mask = $bits(CSR[mstateen1]); - Bits<64> hstateen1_value = csr_value & mstateen1_mask; + Bits<64> hstateen1_value = $bits(CSR[hstateen1]) & mstateen1_mask; return hstateen1_value; diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index bcbf972c4..b0b921017 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -76,5 +76,5 @@ sw_read(): | # appears as read-only zero in the matching hstateen CSR Bits<64> mstateen2_mask = $bits(CSR[mstateen2]); - Bits<64> hstateen2_value = csr_value & mstateen2_mask; + Bits<64> hstateen2_value = $bits(CSR[hstateen2]) & mstateen2_mask; return hstateen2_value; diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index b85c9d666..6fe99df66 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -76,5 +76,5 @@ sw_read(): | # appears as read-only zero in the matching hstateen CSR Bits<64> mstateen3_mask = $bits(CSR[mstateen3]); - Bits<64> hstateen3_value = csr_value & mstateen3_mask; + Bits<64> hstateen3_value = $bits(CSR[hstateen3]) & mstateen3_mask; return hstateen3_value; diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index 7611f2053..8ce5b21f0 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -127,7 +127,7 @@ sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. Bits<64> mstateen0_mask = $bits(CSR[mstateen0]); - Bits<64> sstateen0_value = csr_value & mstateen0_mask; + Bits<64> sstateen0_value = $bits(CSR[sstateen0]) & mstateen0_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index d35c5e8c3..f8c07fea0 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -94,7 +94,7 @@ sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. Bits<64> mstateen1_mask = $bits(CSR[mstateen1]); - Bits<64> sstateen1_value = csr_value & mstateen1_mask; + Bits<64> sstateen1_value = $bits(CSR[sstateen1]) & mstateen1_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. diff --git a/arch/csr/sstateen2.yaml b/arch/csr/sstateen2.yaml index fa5b8e742..b57bd234c 100644 --- a/arch/csr/sstateen2.yaml +++ b/arch/csr/sstateen2.yaml @@ -94,7 +94,7 @@ sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. Bits<64> mstateen2_mask = $bits(CSR[mstateen2]); - Bits<64> sstateen2_value = csr_value & mstateen2_mask; + Bits<64> sstateen2_value = $bits(CSR[sstateen2]) & mstateen2_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index 845e69a7f..c66f8e60d 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -94,7 +94,7 @@ sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. Bits<64> mstateen3_mask = $bits(CSR[mstateen3]); - Bits<64> sstateen3_value = csr_value & mstateen3_mask; + Bits<64> sstateen3_value = $bits(CSR[sstateen3]) & mstateen3_mask; # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. From 5d4e1bec2a3afd3db6c93bed42dcddc9c4f1b51b Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 8 May 2025 18:41:50 +0000 Subject: [PATCH 22/38] docs(stateen): more fixes --- arch/csr/sstateen1.yaml | 2 +- arch/csr/sstateen3.yaml | 2 +- 2 files changed, 2 insertions(+), 2 deletions(-) diff --git a/arch/csr/sstateen1.yaml b/arch/csr/sstateen1.yaml index f8c07fea0..5c93aed6b 100644 --- a/arch/csr/sstateen1.yaml +++ b/arch/csr/sstateen1.yaml @@ -88,7 +88,7 @@ fields: data_value = data_value & hstateen1_mask; } - return data_value + return data_value; reset_value: UNDEFINED_LEGAL sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index c66f8e60d..341adc177 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -88,7 +88,7 @@ fields: data_value = data_value & hstateen3_mask; } - return data_value + return data_value; reset_value: UNDEFINED_LEGAL sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit From 3bc93596664f0182d04a5624de2955c2ecea21bc Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 8 May 2025 18:59:25 +0000 Subject: [PATCH 23/38] docs(stateen): syntax fix --- arch/csr/sstateen3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index 341adc177..11606e5f9 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -84,7 +84,7 @@ fields: # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen3mask = $bits(CSR[hstateen3]); + Bits<64> hstateen_3mask = $bits(CSR[hstateen3]); data_value = data_value & hstateen3_mask; } From a439395de63ecad528a66fc76cf80f61ceac037f Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 8 May 2025 19:05:35 +0000 Subject: [PATCH 24/38] fix --- arch/csr/sstateen3.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/csr/sstateen3.yaml b/arch/csr/sstateen3.yaml index 11606e5f9..accacc25b 100644 --- a/arch/csr/sstateen3.yaml +++ b/arch/csr/sstateen3.yaml @@ -84,7 +84,7 @@ fields: # For every bit in an hstateen CSR that is zero, the same bit # appears as read-only zero in sstateen when accessed in VS-mode. if (mode() == PrivilegeMode::VS) { - Bits<64> hstateen_3mask = $bits(CSR[hstateen3]); + Bits<64> hstateen3_mask = $bits(CSR[hstateen3]); data_value = data_value & hstateen3_mask; } From 7dae65af421c50cf20a5a4b28bda3ba7b267ef2c Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Mon, 12 May 2025 20:26:54 +0000 Subject: [PATCH 25/38] docs(stateen): add params to zcmt --- arch/ext/Zcmt.yaml | 52 ++++++++++++++++++++++++++++++++++++++++++++++ 1 file changed, 52 insertions(+) diff --git a/arch/ext/Zcmt.yaml b/arch/ext/Zcmt.yaml index f3ed2357e..1fd8222a7 100644 --- a/arch/ext/Zcmt.yaml +++ b/arch/ext/Zcmt.yaml @@ -90,3 +90,55 @@ versions: # - [Zcb, "1.0.0"] # - [Zcmp, "1.0.0"] # - [Zcmt, "1.0.0"] + +params: + MSTATEEN_JVT_TYPE: + when: + name: Smstateen + version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the mstateen0.JVT bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + HSTATEEN_JVT_TYPE: + when: + allOf: + - name: H + - version: ~> 1.0 + - name: Ssstateen + - version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the hstateen0.JVT bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + extra_validation: | + assert HSTATEEN_JVT_TYPE == 'read-only-0' if MSTATEEN_JVT_TYPE == 'read-only-0' + assert HSTATEEN_JVT_TYPE == 'read-only-1' if MSTATEEN_JVT_TYPE == 'read-only-1' + SSTATEEN_JVT_TYPE: + when: + allOf: + - name: S + - version: ~> 1.0 + - name: Sstateen + - version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the sstateen0.JVT bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + extra_validation: | + assert SSTATEEN_JVT_TYPE == 'read-only-0' if MSTATEEN_JVT_TYPE == 'read-only-0' + assert SSTATEEN_JVT_TYPE == 'read-only-0' if HSTATEEN_JVT_TYPE == 'read-only-0' + assert SSTATEEN_JVT_TYPE == 'read-only-1' if MSTATEEN_JVT_TYPE == 'read-only-1' + assert SSTATEEN_JVT_TYPE == 'read-only-1' if HSTATEEN_JVT_TYPE == 'read-only-1' From a0d910c3a79b37ffd71e53648fae84bb5f5230ec Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 15 May 2025 19:06:23 +0000 Subject: [PATCH 26/38] docs(stateen): update fields based on newest specs --- arch/csr/hstateen0.yaml | 15 +++++++++++++++ arch/csr/hstateen0h.yaml | 19 +++++++++++++++++++ arch/csr/mstateen0.yaml | 18 ++++++++++++++++++ arch/csr/mstateen0h.yaml | 24 ++++++++++++++++++++++++ 4 files changed, 76 insertions(+) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 662688faa..d775105d7 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -147,6 +147,21 @@ fields: if (CSR[mstateen0].CONTEXT == 1'b0){ return 0; } + CTR: + long_name: ctr access control + location: 54 + base: 64 + description: | + If the H extension is implemented and `mstateen0.CTR=1`, the `hstateen0.CTR` bit controls access to + supervisor CTR state when V=1. This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*` + (really `vsireg*`) when `siselect` (really `vsiselect`) is in 0x200..0x2FF. `hstateen0.CTR` is read-only 0 when + `mstateen0.CTR=0`. + type: RW + reset_value: 0 + sw_write(csr_value): | + if (CSR[mstateen0].CTR == 1'b0){ + return 0; + } JVT: long_name: jvt access control location: 2 diff --git a/arch/csr/hstateen0h.yaml b/arch/csr/hstateen0h.yaml index adf489c52..12872bbbd 100644 --- a/arch/csr/hstateen0h.yaml +++ b/arch/csr/hstateen0h.yaml @@ -139,4 +139,23 @@ fields: by the Sdtrig extension. type: RW reset_value: UNDEFINED_LEGAL + CTR: + long_name: ctr access control + location: 22 + alias: hstateen0.CTR + sw_write(csr_value): | + if (CSR[mstateen0].CTR == 1'b0){ + return 0; + } + else{ + CSR[hstateen0].CTR = csr_value.CTR; + return csr_value.CTR; + } + description: | + If the H extension is implemented and `mstateen0.CTR=1`, the `hstateen0.CTR` bit controls access to + supervisor CTR state when V=1. This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*` + (really `vsireg*`) when `siselect` (really `vsiselect`) is in 0x200..0x2FF. `hstateen0.CTR` is read-only 0 when + `mstateen0.CTR=0`. + type: RW + reset_value: 0 sw_read(): return $bits(CSR[hstateen0])[63:32]; diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index ab449eb20..aaee9c3bb 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -133,6 +133,24 @@ fields: Version 1.13. type: RW reset_value: 0 + SRMCFG: + long_name: srmcfg access control + location: 55 + base: 64 + description: | + The SRMCFG bit in `mstateen0` controls access to the `srmcfg`` CSR introduced by the Ssqosid Chapter 18 + extension. + type: RW + reset_value: 0 + CTR: + long_name: ctr access control + location: 54 + base: 64 + description: | + When Smstateen is implemented, the `mstateen0.CTR` bit controls access to CTR register state from + privilege modes less privileged than M-mode. + type: RW + reset_value: 0 JVT: long_name: jvt access control location: 2 diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml index 068fa56e7..37a3b03de 100644 --- a/arch/csr/mstateen0h.yaml +++ b/arch/csr/mstateen0h.yaml @@ -108,4 +108,28 @@ fields: Version 1.13. type: RW reset_value: 0 + SRMCFG: + long_name: srmcfg access control + location: 23 + alias: mstateen0.SRMCFG + sw_write(csr_value): | + CSR[mstateen0].SRMCFG = csr_value.SRMCFG; + return csr_value.SRMCFG; + description: | + The SRMCFG bit in `mstateen0h` controls access to the `srmcfg`` CSR introduced by the Ssqosid Chapter 18 + extension. + type: RW + reset_value: 0 + CTR: + long_name: ctr access control + location: 22 + alias: mstateen0.CTR + sw_write(csr_value): | + CSR[mstateen0].CTR = csr_value.CTR; + return csr_value.CTR; + description: | + When Smstateen is implemented, the `mstateen0.CTR` bit controls access to CTR register state from + privilege modes less privileged than M-mode. + type: RW + reset_value: 0 sw_read(): return $bits(CSR[mstateen0])[63:32]; From a73ea8ebcfccbfdf0176a5f821483ab523d40d82 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Tue, 20 May 2025 03:11:57 +0000 Subject: [PATCH 27/38] docs(stateen): fix sw_write --- arch/csr/hstateen0.yaml | 10 ++++++++++ arch/csr/hstateen1.yaml | 1 + arch/csr/hstateen2.yaml | 1 + arch/csr/hstateen3.yaml | 1 + arch/csr/sstateen0.yaml | 3 +++ 5 files changed, 16 insertions(+) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index d775105d7..fccd5169f 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -71,6 +71,7 @@ fields: if (CSR[mstateen0].SE0 == 1'b0){ return 0; } + return csr_value.SE0; ENVCFG: long_name: senvcfg access control location: 62 @@ -86,6 +87,7 @@ fields: if (CSR[mstateen0].ENVCFG == 1'b0){ return 0; } + return csr_value.ENVCFG; CSRIND: long_name: siselect and sireg* access control location: 60 @@ -101,6 +103,7 @@ fields: if (CSR[mstateen0].CSRIND == 1'b0){ return 0; } + return csr_value.CSRIND; AIA: long_name: Ssaia state access control location: 59 @@ -116,6 +119,7 @@ fields: if (CSR[mstateen0].AIA == 1'b0){ return 0; } + return csr_value.AIA; IMSIC: long_name: IMSIC state access control location: 58 @@ -133,6 +137,7 @@ fields: if (CSR[mstateen0].IMSIC == 1'b0){ return 0; } + return csr_value.IMSIC; CONTEXT: long_name: scontext access control location: 57 @@ -147,6 +152,7 @@ fields: if (CSR[mstateen0].CONTEXT == 1'b0){ return 0; } + return csr_value.CONTEXT; CTR: long_name: ctr access control location: 54 @@ -162,6 +168,7 @@ fields: if (CSR[mstateen0].CTR == 1'b0){ return 0; } + return csr_value.CTR; JVT: long_name: jvt access control location: 2 @@ -174,6 +181,7 @@ fields: if (CSR[mstateen0].JVT == 1'b0){ return 0; } + return csr_value.JVT; FCSR: long_name: fcsr access control location: 1 @@ -194,6 +202,7 @@ fields: if (CSR[mstateen0].FCSR == 1'b0){ return 0; } + return csr_value.FCSR; C: long_name: custom state access control location: 0 @@ -207,6 +216,7 @@ fields: if (CSR[mstateen0].C == 1'b0){ return 0; } + return csr_value.C; sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index 43b3e19ba..3e238e0c1 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -71,6 +71,7 @@ fields: if (CSR[mstateen1].SE0 == 1'b0){ return 0; } + return csr_value.SE0; sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index b0b921017..680becca1 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -71,6 +71,7 @@ fields: if (CSR[mstateen2].SE0 == 1'b0){ return 0; } + return csr_value.SE0; sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index 6fe99df66..eec937fe9 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -71,6 +71,7 @@ fields: if (CSR[mstateen3].SE0 == 1'b0){ return 0; } + return csr_value.SE0; sw_read(): | # for every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching hstateen CSR diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index 8ce5b21f0..afe0dd0fe 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -84,6 +84,7 @@ fields: else if (mode() == PrivilegeMode::VS && CSR[hstateen0].JVT == 1'b0) { return 0; } + return csr_value.JVT; FCSR: long_name: fcsr access control location: 1 @@ -107,6 +108,7 @@ fields: else if (mode() == PrivilegeMode::VS && CSR[hstateen0].FCSR == 1'b0) { return 0; } + return csr_value.FCSR; C: long_name: custom state access control location: 0 @@ -123,6 +125,7 @@ fields: else if (mode() == PrivilegeMode::VS && CSR[hstateen0].C == 1'b0) { return 0; } + return csr_value.C; sw_read(): | # For every bit in an mstateen CSR that is zero, the same bit # appears as read-only zero in the matching sstateen CSR. From c14d794c88328156d99475aaa23a0743a238f035 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Tue, 20 May 2025 03:27:00 +0000 Subject: [PATCH 28/38] docs(stateen): add params for ext files --- arch/ext/S.yaml | 30 ++++++++++++++++++++ arch/ext/Sdtrig.yaml | 32 ++++++++++++++++++++++ arch/ext/Ssaia.yaml | 62 ++++++++++++++++++++++++++++++++++++++++++ arch/ext/Sscsrind.yaml | 32 ++++++++++++++++++++++ 4 files changed, 156 insertions(+) diff --git a/arch/ext/S.yaml b/arch/ext/S.yaml index 9c73b52ea..4cc97f81b 100644 --- a/arch/ext/S.yaml +++ b/arch/ext/S.yaml @@ -333,3 +333,33 @@ params: When not implemented mstatus.TVM will be read-only-zero. schema: type: boolean + MSTATEEN_ENVCFG_TYPE: + when: + name: Smstateen + version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the mstateen0.ENVCFG bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + HSTATEEN_ENVCFG_TYPE: + when: + allOf: + - name: H + - version: ~> 1.0 + - name: Ssstateen + - version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the hstateen0.ENVCFG bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + extra_validation: | + assert HSTATEEN_ENVCFG_TYPE == 'read-only-0' if MSTATEEN_ENVCFG_TYPE == 'read-only-0' + assert HSTATEEN_ENVCFG_TYPE == 'read-only-1' if MSTATEEN_ENVCFG_TYPE == 'read-only-1' diff --git a/arch/ext/Sdtrig.yaml b/arch/ext/Sdtrig.yaml index 28c25794f..527abac9b 100644 --- a/arch/ext/Sdtrig.yaml +++ b/arch/ext/Sdtrig.yaml @@ -28,3 +28,35 @@ versions: - version: "1.0.0" state: ratified ratification_date: null + +params: + MSTATEEN_CONTEXT_TYPE: + when: + name: Smstateen + version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the mstateen0.CONTEXT bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + HSTATEEN_CONTEXT_TYPE: + when: + allOf: + - name: H + - version: ~> 1.0 + - name: Ssstateen + - version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the hstateen0.CONTEXT bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + extra_validation: | + assert HSTATEEN_CONTEXT_TYPE == 'read-only-0' if MSTATEEN_CONTEXT_TYPE == 'read-only-0' + assert HSTATEEN_CONTEXT_TYPE == 'read-only-1' if MSTATEEN_CONTEXT_TYPE == 'read-only-1' diff --git a/arch/ext/Ssaia.yaml b/arch/ext/Ssaia.yaml index 028adb0fa..97b12f132 100644 --- a/arch/ext/Ssaia.yaml +++ b/arch/ext/Ssaia.yaml @@ -14,3 +14,65 @@ versions: requires: name: S version: ">= 1.12" + +params: + MSTATEEN_AIA_TYPE: + when: + name: Smstateen + version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the mstateen0.AIA bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + HSTATEEN_AIA_TYPE: + when: + allOf: + - name: H + - version: ~> 1.0 + - name: Ssstateen + - version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the hstateen0.AIA bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + extra_validation: | + assert HSTATEEN_AIA_TYPE == 'read-only-0' if MSTATEEN_AIA_TYPE == 'read-only-0' + assert HSTATEEN_AIA_TYPE == 'read-only-1' if MSTATEEN_AIA_TYPE == 'read-only-1' + MSTATEEN_IMSIC_TYPE: + when: + name: Smstateen + version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the mstateen0.IMSIC bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + HSTATEEN_IMSIC_TYPE: + when: + allOf: + - name: H + - version: ~> 1.0 + - name: Ssstateen + - version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the hstateen0.IMSIC bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + extra_validation: | + assert HSTATEEN_IMSIC_TYPE == 'read-only-0' if MSTATEEN_IMSIC_TYPE == 'read-only-0' + assert HSTATEEN_IMSIC_TYPE == 'read-only-1' if MSTATEEN_IMSIC_TYPE == 'read-only-1' diff --git a/arch/ext/Sscsrind.yaml b/arch/ext/Sscsrind.yaml index fba0681d9..3a887295d 100644 --- a/arch/ext/Sscsrind.yaml +++ b/arch/ext/Sscsrind.yaml @@ -42,3 +42,35 @@ versions: version: ~> 1.13 - name: Smcsrind version: ~> 1.0 + +params: + MSTATEEN_CSRIND_TYPE: + when: + name: Smstateen + version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the mstateen0.CSRIND bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + HSTATEEN_CSRIND_TYPE: + when: + allOf: + - name: H + - version: ~> 1.0 + - name: Ssstateen + - version: ~> 1.0 + schema: + enum: [rw, read-only-0, read-only-1] + description: | + Behavior of the hstateen0.CSRIND bit: + + * 'rw': read-write + * 'read-only-0': read-only, fixed to 0 + * 'read-only-1': read-only, fixed to 1 + extra_validation: | + assert HSTATEEN_CSRIND_TYPE == 'read-only-0' if MSTATEEN_CSRIND_TYPE == 'read-only-0' + assert HSTATEEN_CSRIND_TYPE == 'read-only-1' if MSTATEEN_CSRIND_TYPE == 'read-only-1' From 7c06ae7bd34eccdcd99987cd0819c117be69d9d7 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 22 May 2025 16:00:12 +0000 Subject: [PATCH 29/38] docs(stateen): sw_write fixes --- arch/csr/hstateen0h.yaml | 42 ++++++++++++++-------------------------- arch/csr/hstateen1h.yaml | 6 ++---- arch/csr/hstateen2h.yaml | 6 ++---- arch/csr/hstateen3h.yaml | 6 ++---- 4 files changed, 20 insertions(+), 40 deletions(-) diff --git a/arch/csr/hstateen0h.yaml b/arch/csr/hstateen0h.yaml index 12872bbbd..2e05f5ede 100644 --- a/arch/csr/hstateen0h.yaml +++ b/arch/csr/hstateen0h.yaml @@ -35,10 +35,8 @@ fields: if (CSR[mstateen0].SE0 == 1'b0){ return 0; } - else{ - CSR[hstateen0].SE0 = csr_value.SE0; - return csr_value.SE0; - } + CSR[hstateen0].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `hstateen0h` controls access to the `sstateen0` CSR. type: RW @@ -54,10 +52,8 @@ fields: if (CSR[mstateen0].ENVCFG == 1'b0){ return 0; } - else{ - CSR[hstateen0].ENVCFG = csr_value.ENVCFG; - return csr_value.ENVCFG; - } + CSR[hstateen0].ENVCFG = csr_value.ENVCFG; + return csr_value.ENVCFG; description: | The ENVCFG bit in `hstateen0h` controls access to the `senvcfg` CSRs. type: RW @@ -71,10 +67,8 @@ fields: if (CSR[mstateen0].CSRIND == 1'b0){ return 0; } - else{ - CSR[hstateen0].CSRIND = csr_value.CSRIND; - return csr_value.CSRIND; - } + CSR[hstateen0].CSRIND = csr_value.CSRIND; + return csr_value.CSRIND; description: | The CSRIND bit in `hstateen0h` controls access to the `siselect` and the `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind @@ -90,10 +84,8 @@ fields: if (CSR[mstateen0].AIA == 1'b0){ return 0; } - else{ - CSR[hstateen0].AIA = csr_value.AIA; - return csr_value.AIA; - } + CSR[hstateen0].AIA = csr_value.AIA; + return csr_value.AIA; description: | The AIA bit in `hstateen0h` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the @@ -109,10 +101,8 @@ fields: if (CSR[mstateen0].IMSIC == 1'b0){ return 0; } - else{ - CSR[hstateen0].IMSIC = csr_value.IMSIC; - return csr_value.IMSIC; - } + CSR[hstateen0].IMSIC = csr_value.IMSIC; + return csr_value.IMSIC; description: | The IMSIC bit in `hstateen0h` controls access to the guest IMSIC state, including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension. @@ -130,10 +120,8 @@ fields: if (CSR[mstateen0].CONTEXT == 1'b0){ return 0; } - else{ - CSR[hstateen0].CONTEXT = csr_value.CONTEXT; - return csr_value.CONTEXT; - } + CSR[hstateen0].CONTEXT = csr_value.CONTEXT; + return csr_value.CONTEXT; description: | The CONTEXT bit in `hstateen0h` controls access to the `scontext` CSR provided by the Sdtrig extension. @@ -147,10 +135,8 @@ fields: if (CSR[mstateen0].CTR == 1'b0){ return 0; } - else{ - CSR[hstateen0].CTR = csr_value.CTR; - return csr_value.CTR; - } + CSR[hstateen0].CTR = csr_value.CTR; + return csr_value.CTR; description: | If the H extension is implemented and `mstateen0.CTR=1`, the `hstateen0.CTR` bit controls access to supervisor CTR state when V=1. This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*` diff --git a/arch/csr/hstateen1h.yaml b/arch/csr/hstateen1h.yaml index 35874cb49..342591cab 100644 --- a/arch/csr/hstateen1h.yaml +++ b/arch/csr/hstateen1h.yaml @@ -35,10 +35,8 @@ fields: if (CSR[mstateen1].SE0 == 1'b0){ return 0; } - else{ - CSR[hstateen1].SE0 = csr_value.SE0; - return csr_value.SE0; - } + CSR[hstateen1].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `hstateen1h` controls access to the `sstateen1` CSR. type: RW diff --git a/arch/csr/hstateen2h.yaml b/arch/csr/hstateen2h.yaml index b3180b80f..4756be5d2 100644 --- a/arch/csr/hstateen2h.yaml +++ b/arch/csr/hstateen2h.yaml @@ -35,10 +35,8 @@ fields: if (CSR[mstateen2].SE0 == 1'b0){ return 0; } - else{ - CSR[hstateen2].SE0 = csr_value.SE0; - return csr_value.SE0; - } + CSR[hstateen2].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `hstateen2h` controls access to the `sstateen2` CSR. type: RW diff --git a/arch/csr/hstateen3h.yaml b/arch/csr/hstateen3h.yaml index 4ba7c95ba..feb2393e3 100644 --- a/arch/csr/hstateen3h.yaml +++ b/arch/csr/hstateen3h.yaml @@ -35,10 +35,8 @@ fields: if (CSR[mstateen3].SE0 == 1'b0){ return 0; } - else{ - CSR[hstateen3].SE0 = csr_value.SE0; - return csr_value.SE0; - } + CSR[hstateen3].SE0 = csr_value.SE0; + return csr_value.SE0; description: | The SE0 bit in `hstateen3h` controls access to the `sstateen3` CSR. type: RW From c7bba1d1c3a985af821f94c734d9bfb48bd7d043 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 22 May 2025 16:08:30 +0000 Subject: [PATCH 30/38] docs(stateen): add definedBy for some fields --- arch/csr/hstateen0.yaml | 2 +- arch/csr/mstateen0.yaml | 3 ++- arch/csr/mstateen0h.yaml | 1 + arch/csr/sstateen0.yaml | 2 +- 4 files changed, 5 insertions(+), 3 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index fccd5169f..814116fe8 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -186,7 +186,7 @@ fields: long_name: fcsr access control location: 1 #definedBy: - #anyOf: [Zfinx, Zdinx] + #anyOf: [Zhinx, Zfinx, Zdinx] description: | The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index aaee9c3bb..b9193cfd6 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -136,6 +136,7 @@ fields: SRMCFG: long_name: srmcfg access control location: 55 + #definedBy: Ssquosid base: 64 description: | The SRMCFG bit in `mstateen0` controls access to the `srmcfg`` CSR introduced by the Ssqosid Chapter 18 @@ -163,7 +164,7 @@ fields: long_name: fcsr access control location: 1 #definedBy: - #anyOf: [Zfinx, Zdinx] + #anyOf: [Zhinx, Zfinx, Zdinx] description: | The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml index 37a3b03de..88585de48 100644 --- a/arch/csr/mstateen0h.yaml +++ b/arch/csr/mstateen0h.yaml @@ -111,6 +111,7 @@ fields: SRMCFG: long_name: srmcfg access control location: 23 + #definedBy: Ssquosid alias: mstateen0.SRMCFG sw_write(csr_value): | CSR[mstateen0].SRMCFG = csr_value.SRMCFG; diff --git a/arch/csr/sstateen0.yaml b/arch/csr/sstateen0.yaml index afe0dd0fe..00c664dac 100644 --- a/arch/csr/sstateen0.yaml +++ b/arch/csr/sstateen0.yaml @@ -89,7 +89,7 @@ fields: long_name: fcsr access control location: 1 #definedBy: - #anyOf: [Zfinx, Zdinx] + #anyOf: [Zhinx, Zfinx, Zdinx] description: | The FCSR bit controls access to `fcsr` for the case when floating-point instructions operate on `x` registers instead of `f` registers as specified by the Zfinx and related From d565997a8ae35def680b1c938d6af9a47514e82a Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Thu, 22 May 2025 16:12:31 +0000 Subject: [PATCH 31/38] docs(stateen): syntax fixes --- arch/ext/S.yaml | 4 ++-- arch/ext/Sdtrig.yaml | 4 ++-- arch/ext/Ssaia.yaml | 8 ++++---- arch/ext/Sscsrind.yaml | 4 ++-- arch/ext/Zcmt.yaml | 8 ++++---- 5 files changed, 14 insertions(+), 14 deletions(-) diff --git a/arch/ext/S.yaml b/arch/ext/S.yaml index 4cc97f81b..42cb348e4 100644 --- a/arch/ext/S.yaml +++ b/arch/ext/S.yaml @@ -349,9 +349,9 @@ params: when: allOf: - name: H - - version: ~> 1.0 + version: ~> 1.0 - name: Ssstateen - - version: ~> 1.0 + version: ~> 1.0 schema: enum: [rw, read-only-0, read-only-1] description: | diff --git a/arch/ext/Sdtrig.yaml b/arch/ext/Sdtrig.yaml index 527abac9b..e24be3bd7 100644 --- a/arch/ext/Sdtrig.yaml +++ b/arch/ext/Sdtrig.yaml @@ -46,9 +46,9 @@ params: when: allOf: - name: H - - version: ~> 1.0 + version: ~> 1.0 - name: Ssstateen - - version: ~> 1.0 + version: ~> 1.0 schema: enum: [rw, read-only-0, read-only-1] description: | diff --git a/arch/ext/Ssaia.yaml b/arch/ext/Ssaia.yaml index 97b12f132..e5474640f 100644 --- a/arch/ext/Ssaia.yaml +++ b/arch/ext/Ssaia.yaml @@ -32,9 +32,9 @@ params: when: allOf: - name: H - - version: ~> 1.0 + version: ~> 1.0 - name: Ssstateen - - version: ~> 1.0 + version: ~> 1.0 schema: enum: [rw, read-only-0, read-only-1] description: | @@ -62,9 +62,9 @@ params: when: allOf: - name: H - - version: ~> 1.0 + version: ~> 1.0 - name: Ssstateen - - version: ~> 1.0 + version: ~> 1.0 schema: enum: [rw, read-only-0, read-only-1] description: | diff --git a/arch/ext/Sscsrind.yaml b/arch/ext/Sscsrind.yaml index 3a887295d..9b5c2605e 100644 --- a/arch/ext/Sscsrind.yaml +++ b/arch/ext/Sscsrind.yaml @@ -60,9 +60,9 @@ params: when: allOf: - name: H - - version: ~> 1.0 + version: ~> 1.0 - name: Ssstateen - - version: ~> 1.0 + version: ~> 1.0 schema: enum: [rw, read-only-0, read-only-1] description: | diff --git a/arch/ext/Zcmt.yaml b/arch/ext/Zcmt.yaml index 1fd8222a7..b42682279 100644 --- a/arch/ext/Zcmt.yaml +++ b/arch/ext/Zcmt.yaml @@ -108,9 +108,9 @@ params: when: allOf: - name: H - - version: ~> 1.0 + version: ~> 1.0 - name: Ssstateen - - version: ~> 1.0 + version: ~> 1.0 schema: enum: [rw, read-only-0, read-only-1] description: | @@ -126,9 +126,9 @@ params: when: allOf: - name: S - - version: ~> 1.0 + version: ~> 1.0 - name: Sstateen - - version: ~> 1.0 + version: ~> 1.0 schema: enum: [rw, read-only-0, read-only-1] description: | From 0cb9aa9430b569abc59e3f874a261b42b47e9f5b Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Tue, 3 Jun 2025 02:18:26 +0000 Subject: [PATCH 32/38] docs(stateen): fix CI failures --- arch/ext/S.yaml | 2 ++ arch/ext/Sdtrig.yaml | 2 ++ arch/ext/Ssaia.yaml | 4 ++++ arch/ext/Sscsrind.yaml | 2 ++ arch/ext/Zcmt.yaml | 3 +++ 5 files changed, 13 insertions(+) diff --git a/arch/ext/S.yaml b/arch/ext/S.yaml index edfd9cbf7..0d7f308bc 100644 --- a/arch/ext/S.yaml +++ b/arch/ext/S.yaml @@ -333,6 +333,7 @@ params: name: Smstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the mstateen0.ENVCFG bit: @@ -348,6 +349,7 @@ params: - name: Ssstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the hstateen0.ENVCFG bit: diff --git a/arch/ext/Sdtrig.yaml b/arch/ext/Sdtrig.yaml index e24be3bd7..b0523e40a 100644 --- a/arch/ext/Sdtrig.yaml +++ b/arch/ext/Sdtrig.yaml @@ -35,6 +35,7 @@ params: name: Smstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the mstateen0.CONTEXT bit: @@ -50,6 +51,7 @@ params: - name: Ssstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the hstateen0.CONTEXT bit: diff --git a/arch/ext/Ssaia.yaml b/arch/ext/Ssaia.yaml index e5474640f..d11fbe195 100644 --- a/arch/ext/Ssaia.yaml +++ b/arch/ext/Ssaia.yaml @@ -21,6 +21,7 @@ params: name: Smstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the mstateen0.AIA bit: @@ -36,6 +37,7 @@ params: - name: Ssstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the hstateen0.AIA bit: @@ -51,6 +53,7 @@ params: name: Smstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the mstateen0.IMSIC bit: @@ -66,6 +69,7 @@ params: - name: Ssstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the hstateen0.IMSIC bit: diff --git a/arch/ext/Sscsrind.yaml b/arch/ext/Sscsrind.yaml index 9b5c2605e..1954f4538 100644 --- a/arch/ext/Sscsrind.yaml +++ b/arch/ext/Sscsrind.yaml @@ -49,6 +49,7 @@ params: name: Smstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the mstateen0.CSRIND bit: @@ -64,6 +65,7 @@ params: - name: Ssstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the hstateen0.CSRIND bit: diff --git a/arch/ext/Zcmt.yaml b/arch/ext/Zcmt.yaml index b42682279..97a6aebbb 100644 --- a/arch/ext/Zcmt.yaml +++ b/arch/ext/Zcmt.yaml @@ -97,6 +97,7 @@ params: name: Smstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the mstateen0.JVT bit: @@ -112,6 +113,7 @@ params: - name: Ssstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the hstateen0.JVT bit: @@ -130,6 +132,7 @@ params: - name: Sstateen version: ~> 1.0 schema: + type: string enum: [rw, read-only-0, read-only-1] description: | Behavior of the sstateen0.JVT bit: From 6fb0fe9c1ecc85f4acbbc58212f6dfe856e03833 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Wed, 4 Jun 2025 03:54:19 +0000 Subject: [PATCH 33/38] docs(mstateen0): typo fix --- arch/csr/mstateen0.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index b9193cfd6..dc91df1a6 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -136,7 +136,7 @@ fields: SRMCFG: long_name: srmcfg access control location: 55 - #definedBy: Ssquosid + #definedBy: Ssqosid base: 64 description: | The SRMCFG bit in `mstateen0` controls access to the `srmcfg`` CSR introduced by the Ssqosid Chapter 18 From cc5c6696a802dbc3b45bcc501dbd58c99cf4275f Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Wed, 4 Jun 2025 03:55:39 +0000 Subject: [PATCH 34/38] docs(mstateen0): typo fix --- arch/csr/mstateen0h.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/csr/mstateen0h.yaml b/arch/csr/mstateen0h.yaml index 88585de48..036910f19 100644 --- a/arch/csr/mstateen0h.yaml +++ b/arch/csr/mstateen0h.yaml @@ -111,7 +111,7 @@ fields: SRMCFG: long_name: srmcfg access control location: 23 - #definedBy: Ssquosid + #definedBy: Ssqosid alias: mstateen0.SRMCFG sw_write(csr_value): | CSR[mstateen0].SRMCFG = csr_value.SRMCFG; From 780876dd5f141192ee46fca24a488bb45396f001 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Wed, 4 Jun 2025 20:50:00 +0000 Subject: [PATCH 35/38] docs(stateen): change MXLEN to 64 --- arch/csr/hstateen0.yaml | 2 +- arch/csr/hstateen1.yaml | 2 +- arch/csr/hstateen2.yaml | 2 +- arch/csr/hstateen3.yaml | 2 +- arch/csr/mstateen0.yaml | 2 +- arch/csr/mstateen1.yaml | 2 +- arch/csr/mstateen2.yaml | 2 +- arch/csr/mstateen3.yaml | 2 +- 8 files changed, 8 insertions(+), 8 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 814116fe8..118c1ec5b 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -6,7 +6,7 @@ name: hstateen0 long_name: Hypervisor State Enable 0 Register address: 0x60C priv_mode: S -length: MXLEN +length: 64 description: - id: csr-hstateen0-purpose normative: true diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index 3e238e0c1..b480d7808 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -6,7 +6,7 @@ name: hstateen1 long_name: Hypervisor State Enable 1 Register address: 0x60D priv_mode: S -length: MXLEN +length: 64 description: - id: csr-hstateen1-purpose normative: true diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index 680becca1..9612d7822 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -6,7 +6,7 @@ name: hstateen2 long_name: Hypervisor State Enable 2 Register address: 0x60E priv_mode: S -length: MXLEN +length: 64 description: - id: csr-hstateen2-purpose normative: true diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index eec937fe9..8daf97eb4 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -6,7 +6,7 @@ name: hstateen3 long_name: Hypervisor State Enable 3 Register address: 0x60F priv_mode: S -length: MXLEN +length: 64 description: - id: csr-hstateen3-purpose normative: true diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index dc91df1a6..81ae70e97 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -6,7 +6,7 @@ name: mstateen0 long_name: Machine State Enable 0 Register address: 0x30C priv_mode: M -length: MXLEN +length: 64 description: - id: csr-mstateen0-purpose normative: true diff --git a/arch/csr/mstateen1.yaml b/arch/csr/mstateen1.yaml index 1bd314cab..61783408a 100644 --- a/arch/csr/mstateen1.yaml +++ b/arch/csr/mstateen1.yaml @@ -6,7 +6,7 @@ name: mstateen1 long_name: Machine State Enable 1 Register address: 0x30D priv_mode: M -length: MXLEN +length: 64 description: - id: csr-mstateen1-purpose normative: true diff --git a/arch/csr/mstateen2.yaml b/arch/csr/mstateen2.yaml index d51062bc9..845e858df 100644 --- a/arch/csr/mstateen2.yaml +++ b/arch/csr/mstateen2.yaml @@ -6,7 +6,7 @@ name: mstateen2 long_name: Machine State Enable 2 Register address: 0x30E priv_mode: M -length: MXLEN +length: 64 description: - id: csr-mstateen2-purpose normative: true diff --git a/arch/csr/mstateen3.yaml b/arch/csr/mstateen3.yaml index 78f808417..cc2a61881 100644 --- a/arch/csr/mstateen3.yaml +++ b/arch/csr/mstateen3.yaml @@ -6,7 +6,7 @@ name: mstateen3 long_name: Machine State Enable 3 Register address: 0x30F priv_mode: M -length: MXLEN +length: 64 description: - id: csr-mstateen3-purpose normative: true From aef6da9dbc7146c344d4718b1e5a92dd713d1fc6 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Wed, 4 Jun 2025 21:01:13 +0000 Subject: [PATCH 36/38] docs(stateen): fix base --- arch/csr/hstateen0.yaml | 7 ------- arch/csr/hstateen1.yaml | 1 - arch/csr/hstateen2.yaml | 1 - arch/csr/hstateen3.yaml | 1 - arch/csr/mstateen0.yaml | 9 --------- arch/csr/mstateen1.yaml | 1 - arch/csr/mstateen2.yaml | 1 - arch/csr/mstateen3.yaml | 1 - 8 files changed, 22 deletions(-) diff --git a/arch/csr/hstateen0.yaml b/arch/csr/hstateen0.yaml index 118c1ec5b..938628a2a 100644 --- a/arch/csr/hstateen0.yaml +++ b/arch/csr/hstateen0.yaml @@ -62,7 +62,6 @@ fields: SE0: long_name: sstateen0 access control location: 63 - base: 64 description: | The SE0 bit in `hstateen0` controls access to the `sstateen0` CSR. type: RW @@ -78,7 +77,6 @@ fields: definedBy: name: S version: ">= 1.11" - base: 64 description: | The ENVCFG bit in `hstateen0` controls access to the `senvcfg` CSRs. type: RW @@ -92,7 +90,6 @@ fields: long_name: siselect and sireg* access control location: 60 definedBy: Sscsrind - base: 64 description: | The CSRIND bit in `hstateen0` controls access to the `siselect` and the `sireg*`, (really `vsiselect` and `vsireg*`) CSRs provided by the Sscsrind @@ -108,7 +105,6 @@ fields: long_name: Ssaia state access control location: 59 definedBy: Ssaia - base: 64 description: | The AIA bit in `hstateen0` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the @@ -124,7 +120,6 @@ fields: long_name: IMSIC state access control location: 58 definedBy: Ssaia - base: 64 description: | The IMSIC bit in `hstateen0` controls access to the guest IMSIC state, including CSRs `stopei` (really `vstopei`), provided by the Ssaia extension. @@ -142,7 +137,6 @@ fields: long_name: scontext access control location: 57 definedBy: Sdtrig - base: 64 description: | The CONTEXT bit in `hstateen0` controls access to the `scontext` CSR provided by the Sdtrig extension. @@ -156,7 +150,6 @@ fields: CTR: long_name: ctr access control location: 54 - base: 64 description: | If the H extension is implemented and `mstateen0.CTR=1`, the `hstateen0.CTR` bit controls access to supervisor CTR state when V=1. This state includes `sctrctl` (really `vsctrctl`), `sctrstatus`, and `sireg*` diff --git a/arch/csr/hstateen1.yaml b/arch/csr/hstateen1.yaml index b480d7808..d89c32d73 100644 --- a/arch/csr/hstateen1.yaml +++ b/arch/csr/hstateen1.yaml @@ -62,7 +62,6 @@ fields: SE0: long_name: sstateen1 access control location: 63 - base: 64 description: | The SE0 bit in `hstateen1` controls access to the `sstateen1` CSR. type: RW diff --git a/arch/csr/hstateen2.yaml b/arch/csr/hstateen2.yaml index 9612d7822..f9873c385 100644 --- a/arch/csr/hstateen2.yaml +++ b/arch/csr/hstateen2.yaml @@ -62,7 +62,6 @@ fields: SE0: long_name: sstateen2 access control location: 63 - base: 64 description: | The SE0 bit in `hstateen2` controls access to the `sstateen2` CSR. type: RW diff --git a/arch/csr/hstateen3.yaml b/arch/csr/hstateen3.yaml index 8daf97eb4..9c8d4ca76 100644 --- a/arch/csr/hstateen3.yaml +++ b/arch/csr/hstateen3.yaml @@ -62,7 +62,6 @@ fields: SE0: long_name: sstateen3 access control location: 63 - base: 64 description: | The SE0 bit in `hstateen3` controls access to the `sstateen3` CSR. type: RW diff --git a/arch/csr/mstateen0.yaml b/arch/csr/mstateen0.yaml index 81ae70e97..314f9ace2 100644 --- a/arch/csr/mstateen0.yaml +++ b/arch/csr/mstateen0.yaml @@ -68,7 +68,6 @@ fields: SE0: long_name: hstateen0, hstateen0h, and sstateen0 access control location: 63 - base: 64 description: | The SE0 bit in `mstateen0` controls access to the `hstateen0`, `hstateen0h`, and the `sstateen0` CSRs. type: RW @@ -79,7 +78,6 @@ fields: definedBy: name: S version: ">= 1.11" - base: 64 description: | The ENVCFG bit in `mstateen0` controls access to the `henvcfg`, `henvcfgh`, and the `senvcfg` CSRs. type: RW @@ -88,7 +86,6 @@ fields: long_name: siselect, sireg*, vsiselect, and vsireg* access control location: 60 definedBy: Sscsrind - base: 64 description: | The CSRIND bit in `mstateen0` controls access to the `siselect`, `sireg*`, `vsiselect`, and the `vsireg*` CSRs provided by the Sscsrind extensions. @@ -98,7 +95,6 @@ fields: long_name: Ssaia state access control location: 59 definedBy: Ssaia - base: 64 description: | The AIA bit in `mstateen0` controls access to all state introduced by the Ssaia extension and is not controlled by either the CSRIND or the IMSIC bits. @@ -108,7 +104,6 @@ fields: long_name: IMSIC state access control location: 58 definedBy: Ssaia - base: 64 description: | The IMSIC bit in `mstateen0` controls access to the IMSIC state, including CSRs `stopei` and `vstopei`, provided by the Ssaia extension. @@ -118,7 +113,6 @@ fields: long_name: scontext and hcontext access control location: 57 definedBy: Sdtrig - base: 64 description: | The CONTEXT bit in `mstateen0` controls access to the `scontext` and `hcontext` CSRs provided by the Sdtrig extension. @@ -127,7 +121,6 @@ fields: P1P13: long_name: hedelegh access control location: 56 - base: 64 description: | The P1P13 bit in `mstateen0` controls access to the `hedelegh` introduced by Privileged Specification Version 1.13. @@ -137,7 +130,6 @@ fields: long_name: srmcfg access control location: 55 #definedBy: Ssqosid - base: 64 description: | The SRMCFG bit in `mstateen0` controls access to the `srmcfg`` CSR introduced by the Ssqosid Chapter 18 extension. @@ -146,7 +138,6 @@ fields: CTR: long_name: ctr access control location: 54 - base: 64 description: | When Smstateen is implemented, the `mstateen0.CTR` bit controls access to CTR register state from privilege modes less privileged than M-mode. diff --git a/arch/csr/mstateen1.yaml b/arch/csr/mstateen1.yaml index 61783408a..df87b315b 100644 --- a/arch/csr/mstateen1.yaml +++ b/arch/csr/mstateen1.yaml @@ -68,7 +68,6 @@ fields: SE0: long_name: hstateen1, hstateen1h, and sstateen1 access control location: 63 - base: 64 description: | The SE0 bit in `mstateen1` controls access to the `hstateen1`, `hstateen1h`, and the `sstateen1` CSRs. type: RW diff --git a/arch/csr/mstateen2.yaml b/arch/csr/mstateen2.yaml index 845e858df..63b4e8796 100644 --- a/arch/csr/mstateen2.yaml +++ b/arch/csr/mstateen2.yaml @@ -68,7 +68,6 @@ fields: SE0: long_name: hstateen2, hstateen2h, and sstateen2 access control location: 63 - base: 64 description: | The SE0 bit in `mstateen2` controls access to the `hstateen2`, `hstateen2h`, and the `sstateen2` CSRs. type: RW diff --git a/arch/csr/mstateen3.yaml b/arch/csr/mstateen3.yaml index cc2a61881..bb968f417 100644 --- a/arch/csr/mstateen3.yaml +++ b/arch/csr/mstateen3.yaml @@ -68,7 +68,6 @@ fields: SE0: long_name: hstateen3, hstateen3h, and sstateen3 access control location: 63 - base: 64 description: | The SE0 bit in `mstateen3` controls access to the `hstateen3`, `hstateen3h`, and the `sstateen3` CSRs. type: RW From b7e7f706cb560ce6f17076cbb23685b6a806a131 Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Wed, 4 Jun 2025 21:10:32 +0000 Subject: [PATCH 37/38] docs(zcmt): fix Zcmt typo --- arch/ext/Zcmt.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/arch/ext/Zcmt.yaml b/arch/ext/Zcmt.yaml index 97a6aebbb..171c3f0d6 100644 --- a/arch/ext/Zcmt.yaml +++ b/arch/ext/Zcmt.yaml @@ -129,7 +129,7 @@ params: allOf: - name: S version: ~> 1.0 - - name: Sstateen + - name: Ssstateen version: ~> 1.0 schema: type: string From 3d57b11ac12b3c5c015c34e3c0af6a474b87706e Mon Sep 17 00:00:00 2001 From: Katherine Hsu <2katherinehsu@gmail.com> Date: Wed, 4 Jun 2025 22:32:58 +0000 Subject: [PATCH 38/38] fix(stateen): fix ruby code bug --- lib/cfg_arch.rb | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/lib/cfg_arch.rb b/lib/cfg_arch.rb index f60ed1121..16de8bf4b 100644 --- a/lib/cfg_arch.rb +++ b/lib/cfg_arch.rb @@ -430,7 +430,7 @@ def not_prohibited_extension_versions elsif @config.partially_configured? extensions.map(&:versions).flatten.reject { |ext_ver| transitive_prohibited_extension_versions.include?(ext_ver) } else - extensions.map(&:version).flatten + extensions.map(&:versions).flatten end end alias possible_extension_versions not_prohibited_extension_versions