List view

• Deprecate RISC-V Opcodes

  - Prove that UDB -> riscv-opcodes format -> output is identical to riscv-opcodes output - Implement UDB -> output, prove it is identical - Deprecate riscv-opcodes - Migration documentation

  No due date
  0% complete0 open0 closed

• Profile Appendix

  - Name - Synopsis - Extensions (with “option” type) - Instructions added - CSRs added - Versions - Ratification date

  Due by October 1, 2025
  0% complete0 open0 closed

• Extension Appendix

  - Name - Synopsis - Instructions added - CSRs added - Versions - Ratification date

  Due by October 1, 2025
  0% complete0 open0 closed

• CSR Appendix, Phase 2

  Add data that depends on IDL and/or Sail: - Field list - Reset value - Write behavior - Type (RO/RW/…) - Read behavior

  No due date
  0% complete0 open0 closed

• CSR Appendix, Phase 1

  List of every CSR, with the following information: - Name/mnemonic - Long name (“Signed Multiply”) - (Virtual/Indirect) Address - Synopsis - Field list - Location - Defining extension(s)

  Due by October 1, 2025

  •6/18 issues closed
  33% complete12 open6 closed

• Instruction Appendix, Phase 2

  Add the following data to the instruction appendix: - Assembly format - Encoding (w/ names for opcodes) - Decode variable metadata - Instruction format (I/R/…) - Pseudo instructions

  Due by October 1, 2025
  0% complete0 open0 closed

• Instruction appendix, Phase 1

  Phase 1 shall include: - Integration of riscv-isa-manual repo into UDB - Generated ISA Manual PDF with complete instruction appendix - Generated ISA Manual HTML using Antora with complete instruction appendix In the appendix, we will include, for each instruction: - Mnemonic / name - Long name (e.g, "Signed Multiply") - Synopsis - Encoding, without opcode field names - Decode variables (name and position, no 'type') - Defining extension(s) - Defining profile(s)

  Overdue by 2 month(s)

  •

  Due by May 12, 2025

  •3/5 issues closed
  60% complete2 open3 closed