feat(idl): indirect csr support (#594)

* Adds IDL support to lookup a CSR by indirect address
* Removes `CSR[expression]` syntax for CSR direct address lookup
* Adds generated functions to lookup by direct address and read/write
looked-up CSRs
* Adds a writeable field to CSR schemas (rather than depending on direct
address convention)
* Adds CFG option for `test:idl`.

For example:
```
./do test:idl CFG=qc_iu
```

closes #589

---------

Signed-off-by: Derek Hower <134728312+dhower-qc@users.noreply.github.com>

Author: dhower-qc

.pre-commit-config.yaml

@@ -119,6 +119,7 @@ repos:
     rev: v5.0.2
     hooks:
       - id: reuse-lint-file
+        exclude: COMMIT_EDITMSG
 
   - repo: https://github.com/alessandrojcm/commitlint-pre-commit-hook
     rev: v9.22.0

Rakefile

@@ -264,18 +264,15 @@ namespace :test do
     puts "All files validate against their schema"
   end
 
-  task idl: ["#{$root}/.stamps/resolve-rv32.stamp", "#{$root}/.stamps/resolve-rv64.stamp"]  do
-    print "Parsing IDL code for RV32..."
-    cfg_arch32 = cfg_arch_for("rv32")
-    puts "done"
-
-    cfg_arch32.type_check
+  task :idl do
+    cfg = ENV["CFG"]
+    raise "Missing CFG enviornment variable" if cfg.nil?
 
-    print "Parsing IDL code for RV64..."
-    cfg_arch64 = cfg_arch_for("rv64")
+    print "Parsing IDL code for #{cfg}..."
+    cfg_arch = cfg_arch_for(cfg)
     puts "done"
 
-    cfg_arch64.type_check
+    cfg_arch.type_check
 
     puts "All IDL passed type checking"
   end
@@ -442,8 +439,14 @@ namespace :test do
     Rake::Task["test:lib"].invoke
     $logger.info "Running test:schema"
     Rake::Task["test:schema"].invoke
-    $logger.info "Running test:idl"
+    $logger.info "UPDATE: Running test:idl for rv32"
+    ENV["CFG"] = "rv32"
+    Rake::Task["test:idl"].invoke
+    $logger.info "UPDATE: Running test:idl for rv64"
+    ENV["CFG"] = "rv64"
     Rake::Task["test:idl"].invoke
+    $logger.info "UPDATE: Running test:idl for qc_iu"
+    ENV["CFG"] = "qc_iu"
     $logger.info "Running test:inst_encodings"
     Rake::Task["test:inst_encodings"].invoke
     $logger.info "Running test:llvm"

arch/csr/F/fcsr.yaml

@@ -5,6 +5,7 @@ kind: csr
 name: fcsr
 long_name: Floating-point control and status register (`frm` + `fflags`)
 address: 0x003
+writeable: true
 description: |
   The floating-point control and status register, `fcsr`, is a RISC-V
   control and status register (CSR). It is a 32-bit read/write register

arch/csr/H/henvcfg.yaml

@@ -4,6 +4,7 @@ $schema: "csr_schema.json#"
 kind: csr
 name: henvcfg
 address: 0x60A
+writeable: true
 long_name: Hypervisor Environment Configuration
 description: |
   The henvcfg CSR is a 64-bit read/write register that controls certain characteristics of the

arch/csr/H/henvcfgh.yaml

@@ -4,6 +4,7 @@ $schema: "csr_schema.json#"
 kind: csr
 name: henvcfgh
 address: 0x61A
+writeable: true
 base: 32
 long_name: most-significant 32 bits of Hypervisor Environment Configuration
 description: |

arch/csr/H/hgatp.yaml

@@ -102,6 +102,7 @@ description: |
   HFENCE.GVMA instruction (see <<hfence.vma>>) before or
   after writing `hgatp`.
 address: 0x680
+writeable: true
 priv_mode: S
 definedBy: H
 length: SXLEN

arch/csr/H/htimedelta.yaml

@@ -15,6 +15,7 @@ description: |
   `htimedelta` may be used to represent negative time offsets.
 
 address: 0x605
+writeable: true
 priv_mode: S
 definedBy: H
 length: 64

arch/csr/H/htimedeltah.yaml

@@ -8,6 +8,7 @@ description: |
   Upper half of the `htimedelta` CSR.
 
 address: 0x615
+writeable: true
 priv_mode: S
 definedBy: H
 length: 32

arch/csr/H/htinst.yaml

@@ -4,6 +4,7 @@ $schema: "csr_schema.json#"
 kind: csr
 name: htinst
 address: 0x64a
+writeable: true
 long_name: Hypervisor Trap Instruction Register
 description: |
   When a trap is taken into HS-mode, mtinst is written with a value that, if nonzero,

arch/csr/H/htval.yaml

@@ -4,6 +4,7 @@ $schema: "csr_schema.json#"
 kind: csr
 name: htval
 address: 0x643
+writeable: true
 long_name: Hypervisor Trap Value Register
 description: |
   When a trap is taken into HS-mode, htval is written with additional exception-specific information, alongside stval, to assist software in handling the trap.