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ShehrozkashifShehrozkashif
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Merge branch 'main' into H_CSRs
2 parents 6ec7c09 + 612c0ac commit e45b115

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‎Rakefile

Lines changed: 1 addition & 1 deletion
Original file line numberDiff line numberDiff line change
@@ -272,7 +272,7 @@ namespace :test do
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273273
task schema: "#{$root}/.stamps/resolve-_.stamp" do
274274
puts "Checking arch files against schema.."
275-
Architecture.new("#{$root}/gen/resolved_arch/_").validate(show_progress: true)
275+
cfg_arch_for("_").validate(show_progress: true)
276276
puts "All files validate against their schema"
277277
end
278278

‎arch/ext/Sm.yaml

Lines changed: 1 addition & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -404,6 +404,7 @@ params:
404404
minimum: 0
405405
maximum: 0xFFFFFFFFFFFFFFFF
406406
when:
407+
name: Sm
407408
version: ">= 1.12.0"
408409
PMA_GRANULARITY:
409410
description: |

‎arch/inst/C/c.add.yaml

Lines changed: 8 additions & 8 deletions
Original file line numberDiff line numberDiff line change
@@ -5,20 +5,20 @@ kind: instruction
55
name: c.add
66
long_name: Add
77
description: |
8-
Add the value in rs2 to rd, and store the result in rd.
9-
C.ADD expands into `add rd, rd, rs2`.
8+
Add the value in xs2 to xd, and store the result in xd.
9+
C.ADD expands into `add xd, xd, xs2`.
1010
definedBy:
1111
anyOf:
1212
- C
1313
- Zca
14-
assembly: xd, rs2
14+
assembly: xd, xs2
1515
encoding:
1616
match: 1001----------10
1717
variables:
18-
- name: rs2
18+
- name: xs2
1919
location: 6-2
2020
not: 0
21-
- name: rd
21+
- name: xd
2222
location: 11-7
2323
not: 0
2424
access:
@@ -27,9 +27,9 @@ access:
2727
vs: always
2828
vu: always
2929
operation(): |
30-
XReg t0 = X[rd];
31-
XReg t1 = X[rs2];
32-
X[rd] = t0 + t1;
30+
XReg t0 = X[xd];
31+
XReg t1 = X[xs2];
32+
X[xd] = t0 + t1;
3333
3434
# SPDX-SnippetBegin
3535
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎arch/inst/C/c.addw.yaml

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,31 +5,31 @@ kind: instruction
55
name: c.addw
66
long_name: Add word
77
description: |
8-
Add the 32-bit values in rs2 from rd, and store the result in rd.
9-
The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
10-
C.ADDW expands into `addw rd, rd, rs2`.
8+
Add the 32-bit values in xs2 from xd, and store the result in xd.
9+
The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15).
10+
C.ADDW expands into `addw xd, xd, xs2`.
1111
definedBy:
1212
anyOf:
1313
- C
1414
- Zca
1515
base: 64
16-
assembly: xd, rs2
16+
assembly: xd, xs2
1717
encoding:
1818
match: 100111---01---01
1919
variables:
20-
- name: rs2
20+
- name: xs2
2121
location: 4-2
22-
- name: rd
22+
- name: xd
2323
location: 9-7
2424
access:
2525
s: always
2626
u: always
2727
vs: always
2828
vu: always
2929
operation(): |
30-
Bits<32> t0 = X[creg2reg(rd)][31:0];
31-
Bits<32> t1 = X[creg2reg(rs2)][31:0];
32-
X[creg2reg(rd)] = $signed(t0 + t1);
30+
Bits<32> t0 = X[creg2reg(xd)][31:0];
31+
Bits<32> t1 = X[creg2reg(xs2)][31:0];
32+
X[creg2reg(xd)] = $signed(t0 + t1);
3333
3434
# SPDX-SnippetBegin
3535
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎arch/inst/C/c.and.yaml

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,30 +5,30 @@ kind: instruction
55
name: c.and
66
long_name: And
77
description: |
8-
And rd with rs2, and store the result in rd
9-
The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
10-
C.AND expands into `and rd, rd, rs2`.
8+
And xd with xs2, and store the result in xd
9+
The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15).
10+
C.AND expands into `and xd, xd, xs2`.
1111
definedBy:
1212
anyOf:
1313
- C
1414
- Zca
15-
assembly: xd, rs2
15+
assembly: xd, xs2
1616
encoding:
1717
match: 100011---11---01
1818
variables:
19-
- name: rs2
19+
- name: xs2
2020
location: 4-2
21-
- name: rd
21+
- name: xd
2222
location: 9-7
2323
access:
2424
s: always
2525
u: always
2626
vs: always
2727
vu: always
2828
operation(): |
29-
XReg t0 = X[creg2reg(rd)];
30-
XReg t1 = X[creg2reg(rs2)];
31-
X[creg2reg(rd)] = t0 & t1;
29+
XReg t0 = X[creg2reg(xd)];
30+
XReg t1 = X[creg2reg(xs2)];
31+
X[creg2reg(xd)] = t0 & t1;
3232
3333
# SPDX-SnippetBegin
3434
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎arch/inst/C/c.or.yaml

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,30 +5,30 @@ kind: instruction
55
name: c.or
66
long_name: Or
77
description: |
8-
Or rd with rs2, and store the result in rd
9-
The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
10-
C.OR expands into `or rd, rd, rs2`.
8+
Or xd with xs2, and store the result in xd
9+
The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15).
10+
C.OR expands into `or xd, xd, xs2`.
1111
definedBy:
1212
anyOf:
1313
- C
1414
- Zca
15-
assembly: xd, rs2
15+
assembly: xd, xs2
1616
encoding:
1717
match: 100011---10---01
1818
variables:
19-
- name: rs2
19+
- name: xs2
2020
location: 4-2
21-
- name: rd
21+
- name: xd
2222
location: 9-7
2323
access:
2424
s: always
2525
u: always
2626
vs: always
2727
vu: always
2828
operation(): |
29-
XReg t0 = X[creg2reg(rd)];
30-
XReg t1 = X[creg2reg(rs2)];
31-
X[creg2reg(rd)] = t0 | t1;
29+
XReg t0 = X[creg2reg(xd)];
30+
XReg t1 = X[creg2reg(xs2)];
31+
X[creg2reg(xd)] = t0 | t1;
3232
3333
# SPDX-SnippetBegin
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# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎arch/inst/C/c.sub.yaml

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,30 +5,30 @@ kind: instruction
55
name: c.sub
66
long_name: Subtract
77
description: |
8-
Subtract the value in rs2 from rd, and store the result in rd.
9-
The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
10-
C.SUB expands into `sub rd, rd, rs2`.
8+
Subtract the value in xs2 from xd, and store the result in xd.
9+
The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15).
10+
C.SUB expands into `sub xd, xd, xs2`.
1111
definedBy:
1212
anyOf:
1313
- C
1414
- Zca
15-
assembly: xd, rs2
15+
assembly: xd, xs2
1616
encoding:
1717
match: 100011---00---01
1818
variables:
19-
- name: rs2
19+
- name: xs2
2020
location: 4-2
21-
- name: rd
21+
- name: xd
2222
location: 9-7
2323
access:
2424
s: always
2525
u: always
2626
vs: always
2727
vu: always
2828
operation(): |
29-
XReg t0 = X[creg2reg(rd)];
30-
XReg t1 = X[creg2reg(rs2)];
31-
X[creg2reg(rd)] = t0 - t1;
29+
XReg t0 = X[creg2reg(xd)];
30+
XReg t1 = X[creg2reg(xs2)];
31+
X[creg2reg(xd)] = t0 - t1;
3232
3333
# SPDX-SnippetBegin
3434
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎arch/inst/C/c.subw.yaml

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,31 +5,31 @@ kind: instruction
55
name: c.subw
66
long_name: Subtract word
77
description: |
8-
Subtract the 32-bit values in rs2 from rd, and store the result in rd.
9-
The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
10-
C.SUBW expands into `subw rd, rd, rs2`.
8+
Subtract the 32-bit values in xs2 from xd, and store the result in xd.
9+
The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15).
10+
C.SUBW expands into `subw xd, xd, xs2`.
1111
definedBy:
1212
anyOf:
1313
- C
1414
- Zca
1515
base: 64
16-
assembly: xd, rs2
16+
assembly: xd, xs2
1717
encoding:
1818
match: 100111---00---01
1919
variables:
20-
- name: rs2
20+
- name: xs2
2121
location: 4-2
22-
- name: rd
22+
- name: xd
2323
location: 9-7
2424
access:
2525
s: always
2626
u: always
2727
vs: always
2828
vu: always
2929
operation(): |
30-
Bits<32> t0 = X[creg2reg(rd)][31:0];
31-
Bits<32> t1 = X[creg2reg(rs2)][31:0];
32-
X[creg2reg(rd)] = sext(t0 - t1, 31);
30+
Bits<32> t0 = X[creg2reg(xd)][31:0];
31+
Bits<32> t1 = X[creg2reg(xs2)][31:0];
32+
X[creg2reg(xd)] = sext(t0 - t1, 31);
3333
3434
# SPDX-SnippetBegin
3535
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎arch/inst/C/c.xor.yaml

Lines changed: 9 additions & 9 deletions
Original file line numberDiff line numberDiff line change
@@ -5,30 +5,30 @@ kind: instruction
55
name: c.xor
66
long_name: Exclusive Or
77
description: |
8-
Exclusive or rd with rs2, and store the result in rd
9-
The rd and rs2 register indexes should be used as rd+8 and rs2+8 (registers x8-x15).
10-
C.XOR expands into `xor rd, rd, rs2`.
8+
Exclusive or xd with xs2, and store the result in xd
9+
The xd and xs2 register indexes should be used as xd+8 and xs2+8 (registers x8-x15).
10+
C.XOR expands into `xor xd, xd, xs2`.
1111
definedBy:
1212
anyOf:
1313
- C
1414
- Zca
15-
assembly: xd, rs2
15+
assembly: xd, xs2
1616
encoding:
1717
match: 100011---01---01
1818
variables:
19-
- name: rs2
19+
- name: xs2
2020
location: 4-2
21-
- name: rd
21+
- name: xd
2222
location: 9-7
2323
access:
2424
s: always
2525
u: always
2626
vs: always
2727
vu: always
2828
operation(): |
29-
XReg t0 = X[creg2reg(rd)];
30-
XReg t1 = X[creg2reg(rs2)];
31-
X[creg2reg(rd)] = t0 ^ t1;
29+
XReg t0 = X[creg2reg(xd)];
30+
XReg t1 = X[creg2reg(xs2)];
31+
X[creg2reg(xd)] = t0 ^ t1;
3232
3333
# SPDX-SnippetBegin
3434
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎arch/inst/D/fld.yaml

Lines changed: 4 additions & 4 deletions
Original file line numberDiff line numberDiff line change
@@ -3,19 +3,19 @@
33
$schema: inst_schema.json#
44
kind: instruction
55
name: fld
6-
long_name: No synopsis available
6+
long_name: Load Double-precision Floating-Point
77
description: |
88
No description available.
99
definedBy: D
10-
assembly: xd, xs1, imm
10+
assembly: fd, xs1, imm
1111
encoding:
1212
match: -----------------011-----0000111
1313
variables:
1414
- name: imm
1515
location: 31-20
16-
- name: rs1
16+
- name: xs1
1717
location: 19-15
18-
- name: rd
18+
- name: fd
1919
location: 11-7
2020
access:
2121
s: always

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