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Add H csr vsip,hegeie,hideleg,hie,hip,hvip,vsie,vsscratch,hgeip
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‎arch/csr/H/hgeie.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: "csr_schema.json#"
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kind: csr
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name: hgeie
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long_name: Hypervisor Guest External Interrupt Enable Register
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description: |
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The `hgeie` register is an HSXLEN-bit read/write register that contains enable bits
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for the guest external interrupts at this hart. Each bit in `hgeie` corresponds to
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a guest external interrupt and determines whether that interrupt is enabled.
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address: 0x607
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priv_mode: S
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definedBy: H
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length: SXLEN
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fields:
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GEI_0:
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location: 0
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type: RW
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reset_value: 0
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description: |
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Guest External Interrupt 0 enable bit. When set, enables guest external interrupt 0.
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GEI_1:
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location: 1
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type: RW
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reset_value: 0
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description: |
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Guest External Interrupt 1 enable bit. When set, enables guest external interrupt 1.
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GEI_2:
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location: 2
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type: RW
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reset_value: 0
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description: |
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Guest External Interrupt 2 enable bit. When set, enables guest external interrupt 2.
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GEI_3:
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location: 3
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type: RW
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reset_value: 0
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description: |
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Guest External Interrupt 3 enable bit. When set, enables guest external interrupt 3.

‎arch/csr/H/hgeip.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: "csr_schema.json#"
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kind: csr
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name: hgeip
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long_name: Hypervisor Guest External Interrupt Pending Register
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description: |
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The `hgeip` register is an HSXLEN-bit read-only register that indicates pending guest external interrupts for this hart.
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Each bit of `hgeip` corresponds to a guest external interrupt for a virtual machine.
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The register reflects interrupts directed to virtual machines in VS-level and provides an interrupt-pending status.
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address: 0xE12
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priv_mode: S
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definedBy: H
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length: SXLEN
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fields:
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guest_external_interrupts:
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location: 1
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type: RO
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reset_value: 0
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description: |
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Pending guest external interrupt bits. Each bit corresponds to an individual interrupt directed to a virtual machine.
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This register is read-only and the bit values indicate whether a particular interrupt is pending.
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reserved_1_to_hsxlens_minus_1:
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location: 2
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type: RO
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reset_value: 0
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description: |
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Reserved bits. These bits are not writable and must always be read as zero.

‎arch/csr/H/hideleg.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: "csr_schema.json#"
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kind: csr
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name: hideleg
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long_name: Hypervisor Interrupt Delegation Register
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description: |
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Register hideleg is an HSXLEN-bit read/write register that controls delegation of interrupts from HS-mode
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to VS-mode. An interrupt that has been delegated to HS-mode (using mideleg) is further delegated to VS-mode
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if the corresponding hideleg bit is set. Among bits 15:0 of hideleg, bits 10, 6, and 2 (corresponding to the
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standard VS-level interrupts) are writable, and bits 12, 9, 5, and 1 (corresponding to the standard S-level
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interrupts) are read-only zeros.
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address: 0x603
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priv_mode: S
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definedBy: H
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length: SXLEN
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fields:
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SSIP:
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location: 1
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type: RO
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reset_value: 0
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description: Standard S-level interrupt. Read-only zero.
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VSIP:
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location: 2
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type: RW
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reset_value: 0
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description: Virtual Supervisor Software Interrupt.
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STIP:
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location: 5
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type: RO
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reset_value: 0
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description: Standard S-level interrupt. Read-only zero.
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VSTIP:
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location: 6
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type: RW
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reset_value: 0
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description: Virtual Supervisor Timer Interrupt.
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SEIP:
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location: 9
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type: RO
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reset_value: 0
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description: Standard S-level interrupt. Read-only zero.
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VSEIP:
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location: 10
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type: RW
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reset_value: 0
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description: Virtual Supervisor External Interrupt.
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LCOFIP:
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location: 13
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type: RW
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reset_value: 0
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description: Local Counter Overflow Interrupt.

‎arch/csr/H/hie.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: "csr_schema.json#"
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kind: csr
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name: hie
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long_name: Hypervisor Interrupt Enable Register
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description: |
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The `hie` register is a read/write register in HS-mode that enables interrupts.
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It corresponds to the enable bits for VS-level and hypervisor-specific interrupts, and supplements
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the HS-level `sie` register.
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address: 0x604
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priv_mode: S
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definedBy: H
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length: SXLEN
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fields:
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SGEIE:
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location: 0
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type: RW-H
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reset_value: 0
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description: |
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Hypervisor guest external interrupt enable bit. When set, allows external interrupts to be delivered
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to VS-mode based on the `hgeie` setting.
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VSEIE:
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location: 4
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type: RW-H
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reset_value: 0
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description: |
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VS-level external interrupt enable bit. When set, allows external interrupts directed to VS-level
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to be processed based on the configuration in `hvip` and other platform-specific sources.
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VSTIE:
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location: 8
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type: RW-H
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reset_value: 0
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description: |
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VS-level timer interrupt enable bit. When set, allows VS-level timer interrupts to be processed
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based on the `hvip` configuration and any platform-specific timer interrupts.
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VSSIE:
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location: 12
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type: RW-H
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reset_value: 0
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description: |
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VS-level software interrupt enable bit. When set, allows software interrupts directed to VS-level
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to be processed, based on the configuration in `hvip`.
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reserved:
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location: 13-15
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type: RO
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reset_value: 0
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description: |
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Reserved bits, must always be zero.

‎arch/csr/H/hip.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: "csr_schema.json#"
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kind: csr
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name: hip
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long_name: Hypervisor Interrupt Pending Register
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description: |
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The `hip` register is an HSXLEN-bit read/write register that indicates pending interrupts at the hypervisor level.
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It contains interrupt-pending bits for both VS-level and hypervisor-specific interrupts.
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address: 0x608
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priv_mode: S
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definedBy: H
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length: SXLEN
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fields:
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SGEIP:
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location: 0
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type: RO
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reset_value: 0
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description: |
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Pending interrupt bit for supervisor guest external interrupts (SGEI).
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This bit is 1 if and only if the logical AND of `hgeip` and `hgeie` is nonzero.
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VSEIP:
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location: 1
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type: RO
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reset_value: 0
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description: |
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Pending interrupt bit for VS-level external interrupts (VSEI).
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This bit is the logical OR of `vseip` from `hvip`, the interrupt from `hgeip` selected by `hstatus.VGEIN`,
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and any other external interrupt signal directed to VS-level.
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VSTIP:
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location: 3
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type: RO
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reset_value: 0
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description: |
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Pending interrupt bit for VS-level timer interrupts (VSTI).
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This bit is the logical OR of `vstip` from `hvip` and any other timer interrupt directed to VS-level.
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VSSIP:
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location: 5
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type: RO
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reset_value: 0
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description: |
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Pending interrupt bit for VS-level software interrupts (VSSI).
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This bit is an alias of the `vssip` bit in `hvip`.

‎arch/csr/H/hvip.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: "csr_schema.json#"
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kind: csr
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name: hvip
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long_name: Hypervisor Virtual Interrupt Pending Register
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description: |
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The `hvip` register is an HSXLEN-bit read/write register that a hypervisor can write to indicate virtual interrupts intended for VS-mode.
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It contains interrupt-pending bits for virtual interrupts such as VS-level external interrupts, timer interrupts, and software interrupts.
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address: 0x645
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priv_mode: S
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definedBy: H
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length: SXLEN
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fields:
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VSEIP:
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location: 1
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type: RW
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reset_value: 0
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description: |
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Pending interrupt bit for VS-level external interrupts. This bit is writable and
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is set to 1 to assert a VS-level external interrupt.
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VSTIP:
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location: 3
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type: RW
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reset_value: 0
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description: |
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Pending interrupt bit for VS-level timer interrupts. This bit is writable and
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is set to 1 to assert a VS-level timer interrupt.
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VSSIP:
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location: 5
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type: RW
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reset_value: 0
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description: |
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Pending interrupt bit for VS-level software interrupts. This bit is writable and
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is set to 1 to assert a VS-level software interrupt.
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reserved_6_15:
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location: 6
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type: RO
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reset_value: 0
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description: |
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Reserved bits. These bits must always be zero and are not writable.

‎arch/csr/H/vsie.yaml

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# yaml-language-server: $schema=../../../schemas/csr_schema.json
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$schema: "csr_schema.json#"
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kind: csr
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name: vsie
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address: 0x204
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virtual_address: 0x144
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long_name: Virtual Supervisor Interrupt Enable
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description: |
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The vsie register is a VSXLEN-bit read/write register that is VS-mode’s version of
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supervisor CSR sie. When V=1, vsie substitutes for the usual sie, so instructions that
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normally read or modify sie actually access vsie instead. However, interrupts directed to
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HS-level continue to be indicated in the HS-level sip register, not in vsip, when V=1.
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The standard portion (bits 15:0) of vsie is formatted as follows:
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15 14 13 12 10 9 8 6 5 4 2 1 0
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0 LCOFIE 0 SEIE 0 STIE 0 SSIE 0
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2 1 3 1 3 1 3 1 1
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When bit 13 of hideleg is zero, vsie.LCOFIE is read-only zero. Else, vsie.LCOFIE is an alias of sie.LCOFIE.
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When bit 10 of hideleg is zero, vsie.SEIE is read-only zero. Else, vsie.SEIE is an alias of hie.VSEIE.
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When bit 6 of hideleg is zero, vsie.STIE is read-only zero. Else, vsie.STIE is an alias of hie.VSTIE.
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When bit 2 of hideleg is zero, vsie.SSIE is read-only zero. Else, vsie.SSIE is an alias of hie.VSSIE.
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priv_mode: VS
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definedBy: H
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length: VSXLEN
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fields:
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SSIE:
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location: 1
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type: RW-H
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reset_value: UNDEFINED_LEGAL
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alias: hie.VSSIE[0]
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description: |
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SSIE. Read-only zero when hideleg[2] is 0. Else, alias of hie.VSSIE.
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STIE:
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location: 5
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type: RW-H
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reset_value: UNDEFINED_LEGAL
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alias: hie.VSTIE[0]
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description: |
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STIE. Read-only zero when hideleg[6] is 0. Else, alias of hie.VSTIE.
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SEIE:
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location: 9
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type: RW-H
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reset_value: UNDEFINED_LEGAL
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alias: hie.VSEIE[0]
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description: |
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SEIE. Read-only zero when hideleg[10] is 0. Else, alias of hie.VSEIE.
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LCOFIE:
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location: 13
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type: RW-H
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reset_value: UNDEFINED_LEGAL
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alias: sie.LCOFIE[0]
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description: |
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LCOFIE. Read-only zero when hideleg[13] is 0. Else, alias of sie.LCOFIE.

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