Skip to content

Commit 805159a

Browse files
ayosherayosher
authored
Xqci: 0.13 changes (#839)
changes: - Fix version history of releases v0.11.0 and v0.12.0 - Fix description and IDL code of qc.csrrwr instruction to allow just read CSR --------- Signed-off-by: Albert Yosher <181945086+ayosher@users.noreply.github.com>
1 parent 48cbf1b commit 805159a

File tree

5 files changed

+76
-8
lines changed

5 files changed

+76
-8
lines changed

‎arch_overlay/qc_iu/ext/Xqci.yaml

Lines changed: 38 additions & 2 deletions
Original file line numberDiff line numberDiff line change
@@ -385,7 +385,7 @@ versions:
385385
- { name: Xqcili, version: "0.2.0" }
386386
- { name: Xqcilia, version: "0.2.0" }
387387
- { name: Xqcilo, version: "0.3.0" }
388-
- { name: Xqcilsm, version: "0.6.0" }
388+
- { name: Xqcilsm, version: "0.5.0" }
389389
- { name: Xqcisim, version: "0.2.0" }
390390
- { name: Xqcisls, version: "0.2.0" }
391391
- { name: Xqcisync, version: "0.3.0" }
@@ -421,7 +421,43 @@ versions:
421421
- { name: Xqcili, version: "0.2.0" }
422422
- { name: Xqcilia, version: "0.2.0" }
423423
- { name: Xqcilo, version: "0.3.0" }
424-
- { name: Xqcilsm, version: "0.5.0" }
424+
- { name: Xqcilsm, version: "0.6.0" }
425+
- { name: Xqcisim, version: "0.2.0" }
426+
- { name: Xqcisls, version: "0.2.0" }
427+
- { name: Xqcisync, version: "0.3.0" }
428+
requires:
429+
name: Zca
430+
version: ">= 1.0.0"
431+
- version: "0.13.0"
432+
state: frozen
433+
ratification_date: null
434+
contributors:
435+
- name: Albert Yosher
436+
company: Qualcomm Technologies, Inc.
437+
email: ayosher@qti.qualcomm.com
438+
- name: Derek Hower
439+
company: Qualcomm Technologies, Inc.
440+
email: dhower@qti.qualcomm.com
441+
changes:
442+
- Fix version history of releases v0.11.0 and v0.12.0
443+
- Fix description and IDL code of qc.csrrwr instruction to allow just read CSR
444+
- Fix IDL code of qc.c.mileaveret instruction to avoid restoring from stack NMIP and EXCP bits
445+
implies:
446+
- { name: Xqcia, version: "0.7.0" }
447+
- { name: Xqciac, version: "0.3.0" }
448+
- { name: Xqcibi, version: "0.2.0" }
449+
- { name: Xqcibm, version: "0.8.0" }
450+
- { name: Xqcicli, version: "0.3.0" }
451+
- { name: Xqcicm, version: "0.2.0" }
452+
- { name: Xqcics, version: "0.2.0" }
453+
- { name: Xqcicsr, version: "0.4.0" }
454+
- { name: Xqciint, version: "0.10.0" }
455+
- { name: Xqciio, version: "0.1.0" }
456+
- { name: Xqcilb, version: "0.2.0" }
457+
- { name: Xqcili, version: "0.2.0" }
458+
- { name: Xqcilia, version: "0.2.0" }
459+
- { name: Xqcilo, version: "0.3.0" }
460+
- { name: Xqcilsm, version: "0.6.0" }
425461
- { name: Xqcisim, version: "0.2.0" }
426462
- { name: Xqcisls, version: "0.2.0" }
427463
- { name: Xqcisync, version: "0.3.0" }

‎arch_overlay/qc_iu/ext/Xqcicsr.yaml

Lines changed: 12 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -40,6 +40,18 @@ versions:
4040
email: dhower@qti.qualcomm.com
4141
changes:
4242
- Remove qc.flags CSR
43+
- version: "0.4.0"
44+
state: frozen
45+
ratification_date: null
46+
contributors:
47+
- name: Albert Yosher
48+
company: Qualcomm Technologies, Inc.
49+
email: ayosher@qti.qualcomm.com
50+
- name: Derek Hower
51+
company: Qualcomm Technologies, Inc.
52+
email: dhower@qti.qualcomm.com
53+
changes:
54+
- Fix description and IDL code of qc.csrrwr instruction to allow just read CSR
4355
description: |
4456
The Xqcicsr extension contains two instructions to read/write CSR which index is in register and not immediate.
4557

‎arch_overlay/qc_iu/ext/Xqciint.yaml

Lines changed: 13 additions & 0 deletions
Original file line numberDiff line numberDiff line change
@@ -134,6 +134,19 @@ versions:
134134
changes:
135135
- Fix desciption of qc.c.eir instruction to match IDL code and functionality
136136
requires: { name: Zca, version: ">= 1.0.0" }
137+
- version: "0.10.0"
138+
state: frozen
139+
ratification_date: null
140+
contributors:
141+
- name: Albert Yosher
142+
company: Qualcomm Technologies, Inc.
143+
email: ayosher@qti.qualcomm.com
144+
- name: Derek Hower
145+
company: Qualcomm Technologies, Inc.
146+
email: dhower@qti.qualcomm.com
147+
changes:
148+
- Fix IDL code of qc.c.mileaveret instruction to avoid restoring from stack NMIP and EXCP bits
149+
requires: { name: Zca, version: ">= 1.0.0" }
137150
description: |
138151
The Xqciint extension includes eleven instructions to accelerate interrupt
139152
servicing by performing common actions during ISR prologue/epilogue.

‎arch_overlay/qc_iu/inst/Xqci/qc.c.mileaveret.yaml

Lines changed: 6 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -27,8 +27,11 @@ operation(): |
2727
XReg prev_retpc = read_memory<32>(virtual_address - 4, $encoding);
2828
XReg qc_mcause_val = read_memory<32>(virtual_address - 12, $encoding);
2929
Bits<1> nmie_val = CSR[mnstatus].NMIE;
30+
XReg qc_mcause_prev_val = CSR[qc.mcause].sw_read();
31+
XReg qc_mcause_nmip_excp_mask = (32'b1 << 24) | (32'b1 << 25);
32+
XReg qc_mcause_new_val = (qc_mcause_val & ~qc_mcause_nmip_excp_mask) | (qc_mcause_prev_val & qc_mcause_nmip_excp_mask);
33+
CSR[qc.mcause].sw_write(qc_mcause_new_val);
3034
X[ 8] = read_memory<32>(virtual_address - 8, $encoding);
31-
CSR[qc.mcause].sw_write(qc_mcause_val);
3235
X[ 1] = read_memory<32>(virtual_address - 16, $encoding);
3336
X[ 5] = read_memory<32>(virtual_address - 24, $encoding);
3437
X[ 6] = read_memory<32>(virtual_address - 28, $encoding);
@@ -47,7 +50,7 @@ operation(): |
4750
X[31] = read_memory<32>(virtual_address - 80, $encoding);
4851
X[2] = X[2] + 96;
4952
if (nmie_val == 1'b1) {
50-
XReg qc_mcause_val_masked = qc_mcause_val & ~(32'b1<<26) & ~(32'b1<<27) & ~(32'b1<<29) & ~(32'hFF<<12);
53+
XReg qc_mcause_val_masked = qc_mcause_new_val & ~(32'b1<<26) & ~(32'b1<<27) & ~(32'b1<<29) & ~(32'hFF<<12);
5154
Bits<1> mpie_val = (qc_mcause_val >> 27) & 1;
5255
Bits<1> mpdt_val = (qc_mcause_val >> 29) & 1;
5356
Bits<4> mpil_val = (qc_mcause_val >> 16) & 0xF;
@@ -74,7 +77,7 @@ operation(): |
7477
}
7578
$pc = CSR[mepc].sw_read();
7679
} else {
77-
XReg qc_mcause_val_masked = qc_mcause_val & ~(32'b1<<26) & ~(32'b1<<28) & ~(32'b1<<30) & ~(32'b1111<<12) & ~(32'b1111<<20);
80+
XReg qc_mcause_val_masked = qc_mcause_new_val & ~(32'b1<<26) & ~(32'b1<<28) & ~(32'b1<<30) & ~(32'b1111<<12) & ~(32'b1111<<20);
7881
Bits<1> mnpie_val = (qc_mcause_val >> 28) & 1;
7982
Bits<4> mnpil_val = (qc_mcause_val >> 20) & 0xF;
8083
CSR[mstatus].MIE = mnpie_val;

‎arch_overlay/qc_iu/inst/Xqci/qc.csrrwr.yaml

Lines changed: 7 additions & 3 deletions
Original file line numberDiff line numberDiff line change
@@ -12,6 +12,8 @@ description: |
1212
The initial value in `rs1` is written to the CSR.
1313
If `rd`=`x0`, then the instruction shall not read the CSR and shall not
1414
cause any of the side effects that might occur on a CSR read.
15+
If `rs1`=`x0`, then the instruction shall not write to the CSR and shall not
16+
cause any of the side effects that might occur on a CSR write.
1517
Instruction encoded in R instruction format.
1618
definedBy:
1719
anyOf:
@@ -40,6 +42,8 @@ operation(): |
4042
if (rd != 0) {
4143
X[rd] = csr_sw_read(csr);
4244
}
43-
# writes the value in X[rs1] to the CSR,
44-
# performing any WARL transformations first
45-
csr_sw_write(csr, X[rs1]);
45+
if (rs1 != 0) {
46+
# writes the value in X[rs1] to the CSR,
47+
# performing any WARL transformations first
48+
csr_sw_write(csr, X[rs1]);
49+
}

0 commit comments

Comments
 (0)