Merge branch 'main' into H_CSRs

Author: Shehrozkashif

.vscode/launch.json

@@ -111,10 +111,10 @@
     },
     {
       "type": "rdbg",
-      "name": "RVA20",
+      "name": "RVI20",
       "request": "launch",
       "command": "bundle exec rake",
-      "script": "gen:profile_release_pdf[RVA20]",
+      "script": "gen:profile_release_pdf[RVI20]",
       "args": [],
       "askParameters": false
     },

Rakefile

@@ -388,6 +388,15 @@ file "#{$root}/arch/csr/S/scounteren.yaml" => [
   File.write(t.name, insert_warning(erb.result(binding), t.prerequisites.first))
 end
 
+file "#{$root}/arch/csr/Sscofpmf/scountovf.yaml" => [
+  "#{$root}/arch/csr/Sscofpmf/scountovf.layout",
+  __FILE__
+] do |t|
+  erb = ERB.new(File.read($root / "arch/csr/Sscofpmf/scountovf.layout"), trim_mode: "-")
+  erb.filename = "#{$root}/arch/csr/Sscofpmf/scountovf.layout"
+  File.write(t.name, insert_warning(erb.result(binding), t.prerequisites.first))
+end
+
 file "#{$root}/arch/csr/H/hcounteren.yaml" => [
   "#{$root}/arch/csr/H/hcounteren.layout",
   __FILE__
@@ -421,6 +430,7 @@ namespace :gen do
 
     Rake::Task["#{$root}/arch/csr/I/mcounteren.yaml"].invoke
     Rake::Task["#{$root}/arch/csr/S/scounteren.yaml"].invoke
+    Rake::Task["#{$root}/arch/csr/Sscofpmf/scountovf.yaml"].invoke
     Rake::Task["#{$root}/arch/csr/H/hcounteren.yaml"].invoke
     Rake::Task["#{$root}/arch/csr/Zicntr/mcountinhibit.yaml"].invoke
 

arch/csr/Sscofpmf/scountovf.layout

@@ -0,0 +1,58 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+
+$schema: csr_schema.json#
+kind: csr
+name: scountovf
+long_name: Supervisor Count Overflow
+address: 0xDA0
+priv_mode: S
+length: 32
+definedBy: Sscofpmf
+description: |
+  A 32-bit read-only register that contains shadow copies of the OF bits in the 29 `mhpmevent` CSRs
+  (`mhpmevent3` - `mhpmevent31`) — where `scountovf` bit X corresponds to `mhpmeventX`.
+
+  This register enables supervisor-level overflow interrupt handler
+  software to quickly and easily determine which counter(s) have overflowed
+  without needing to make an execution environment call up to M-mode.
+
+  Read access to bit X is subject to the same `mcounteren` (or `mcounteren` and `hcounteren`)
+  CSRs that mediate access to the `hpmcounter` CSRs by S-mode (or VS-mode).
+
+  In M-mode, `scountovf` bit X is always readable.
+  In S/HS-mode, `scountovf` bit X is readable when `mcounteren` bit X is set, and otherwise reads as zero.
+  Similarly, in VS-mode, it is readable when both `mcounteren` and `hcounteren` bit X are set.
+
+fields:
+<%- (3..31).each do |of_num| -%>
+  OF<%= of_num %>:
+    alias: mhpmevent<%= of_num %>.OF
+    location: <%= of_num %>
+    description: |
+      [when="HPM_COUNTER_EN[<%= of_num %>] == true"]
+      Shadow copy of mhpmevent<%= of_num %> overflow (OF) bit.
+
+      [when="HPM_COUNTER_EN[<%= of_num %>] == false"]
+      This field is read-only zero because the counter is not enabled.
+    type(): |
+      return HPM_COUNTER_EN[<%= of_num %>] ? CsrFieldType::RO : CsrFieldType::ROH;
+    reset_value(): |
+      return HPM_COUNTER_EN[<%= of_num %>] ? UNDEFINED_LEGAL : 0;
+<%- end -%>
+
+sw_read(): |
+  Bits<32> mask;
+  if (mode() == PrivilegeMode::VS) {
+    # In VS-mode, scountovf.OFX access is determined by mcounteren/hcounteren
+    mask = $bits(CSR[mcounteren]) & $bits(CSR[hcounteren]);
+  } else {
+    # In M-mode and S-mode, scountovf.OFX access is determined by mcounteren/scounteren
+    mask = $bits(CSR[mcounteren]) & $bits(CSR[scounteren]);
+  }
+
+  Bits<32> value = 0;
+  <%- (3..31).each do |num| -%>
+    value = value | (CSR[mhpmevent<%= num %>].OF << <%= num %>);
+  <%- end -%>
+
+  return value & mask;