Merge branch 'main' into H_CSRs

Author: Shehrozkashif

.pre-commit-config.yaml

@@ -46,30 +46,47 @@ repos:
     rev: 0.33.0
     hooks:
       - id: check-jsonschema
+        name: Validate instruction files with jsonschema
         stages: [pre-commit]
         alias: check-jsonschema-inst
         files: ^arch/inst/.*\.(yaml|yml)$
         args: ["--schemafile", "schemas/inst_schema.json"]
       - id: check-jsonschema
+        name: Validate CSR files with jsonschema
         stages: [pre-commit]
         alias: check-jsonschema-csr
         files: ^arch/csr/.*\.(yaml|yml)$
         args: ["--schemafile", "schemas/csr_schema.json"]
       - id: check-jsonschema
+        name: Validate extension files with jsonschema
         stages: [pre-commit]
         alias: check-jsonschema-ext
         files: ^arch/ext/.*\.(yaml|yml)$
         args: ["--schemafile", "schemas/ext_schema.json"]
       - id: check-jsonschema
+        name: Validate cert model files with jsonschema
         stages: [pre-commit]
         alias: check-jsonschema-cert-model
         files: ^arch/proc_cert_model/.*\.(yaml|yml)$
         args: ["--schemafile", "schemas/proc_cert_model_schema.json"]
       - id: check-jsonschema
+        name: Validate cert class files with jsonschema
         stages: [pre-commit]
         alias: check-jsonschema-cert-class
         files: ^arch/proc_cert_class/.*\.(yaml|yml)$
         args: ["--schemafile", "schemas/proc_cert_class_schema.json"]
+      - id: check-jsonschema
+        name: Validate profile family files with jsonschema
+        stages: [pre-commit]
+        alias: check-jsonschema-profile-family
+        files: ^arch/profile_family/.*\.(yaml|yml)$
+        args: ["--schemafile", "schemas/profile_family_schema.json"]
+      - id: check-jsonschema
+        name: Validate profile release files with jsonschema
+        stages: [pre-commit]
+        alias: check-jsonschema-profile-release
+        files: ^arch/profile_release/.*\.(yaml|yml)$
+        args: ["--schemafile", "schemas/profile_release_schema.json"]
       # Commenting because throwing errors and not sure this is complete yet
       # - id: check-jsonschema
       #   alias: check-jsonschema-manual-version

arch/csr/H/vsie.yaml

@@ -37,6 +37,23 @@ description:
 priv_mode: VS
 definedBy: H
 length: VSXLEN
+
+sw_read(): |
+  let value = 0;
+  if (CSR[hideleg][2]) {
+      value |= (CSR[hie].VSSIE[0] << 1);
+  }
+  if (CSR[hideleg][6]) {
+      value |= (CSR[hie].VSTIE[0] << 5);
+  }
+  if (CSR[hideleg][10]) {
+      value |= (CSR[hie].VSEIE[0] << 9);
+  }
+  if (CSR[hideleg][13]) {
+      value |= (CSR[sie].LCOFIE[0] << 13);
+  }
+  return value;
+
 fields:
   SSIE:
     location: 1
@@ -45,23 +62,22 @@ fields:
     alias: hie.VSSIE[0]
     description: |
       SSIE. Read-only zero when hideleg[2] is 0. Else, alias of hie.VSSIE.
-      sw_read(): |
-          if (CSR[hideleg].S == 1) {
-            return CSR[hie].VSSIE[0];
-          } else {
-            return 0;
-          }
-      sw_write(csr_value): |
-      if (CSR[hideleg].S == 1) {
-        CSR[hie].VSSIE[0] = csr_value.VSSIE & ((1 << NUM_VSSI) - 1);
+    "sw_write(csr_value)": |
+      if (CSR[hideleg][2]) {
+          CSR[hie].VSSIE[0] = (csr_value >> 1) & 1;
       }
+
   STIE:
     location: 5
     type: RW-H
     reset_value: UNDEFINED_LEGAL
     alias: hie.VSTIE[0]
     description: |
       STIE. Read-only zero when hideleg[6] is 0. Else, alias of hie.VSTIE.
+    "sw_write(csr_value)": |
+      if (CSR[hideleg][6]) {
+          CSR[hie].VSTIE[0] = (csr_value >> 5) & 1;
+      }
 
   SEIE:
     location: 9
@@ -70,6 +86,10 @@ fields:
     alias: hie.VSEIE[0]
     description: |
       SEIE. Read-only zero when hideleg[10] is 0. Else, alias of hie.VSEIE.
+    "sw_write(csr_value)": |
+      if (CSR[hideleg][10]) {
+          CSR[hie].VSEIE[0] = (csr_value >> 9) & 1;
+      }
 
   LCOFIE:
     location: 13
@@ -78,3 +98,7 @@ fields:
     alias: sie.LCOFIE[0]
     description: |
       LCOFIE. Read-only zero when hideleg[13] is 0. Else, alias of sie.LCOFIE.
+    "sw_write(csr_value)": |
+      if (CSR[hideleg][13]) {
+          CSR[sie].LCOFIE[0] = (csr_value >> 13) & 1;
+      }

arch/csr/H/vsip.yaml

@@ -27,6 +27,22 @@ description:
 priv_mode: VS
 definedBy: H
 length: VSXLEN
+sw_read(): |
+  val = 0;
+  if (CSR[hideleg].S == 1) {
+    val |= (CSR[hip].VSSIP[0] << 1);
+  }
+  if (CSR[hideleg].ST == 1) {
+    val |= (CSR[hip].VSTIP[0] << 5);
+  }
+  if (CSR[hideleg].SE == 1) {
+    val |= (CSR[hip].VSEIP[0] << 9);
+  }
+  if (CSR[hideleg].LCOF == 1) {
+    val |= (CSR[sip].LCOFIP[0] << 13);
+  }
+  return val;
+
 fields:
   SSIP:
     location: 1
@@ -35,29 +51,26 @@ fields:
     alias: hip.VSSIP[0]
     description: |
       *Supervisor Software Interrupt Pending*
-
       Indicates a pending software interrupt at the supervisor level.
       Read-only zero when `hideleg[2] == 0`, else aliased to `hip.VSSIP[0]`.
-      sw_read(): |
-        if (CSR[hideleg].S == 1) {
-          return CSR[hip].VSSIP[0];
-        } else {
-          return 0;
-        }
-       sw_write(csr_value): |
-          if (CSR[hideleg].S == 1) {
-            CSR[hip].VSSIP[0] = csr_value.VSSIP & ((MXLEN'1 << NUM_VSSI) - 1);
-        }
+    "sw_write(csr_value)": |
+      if (CSR[hideleg].S == 1) {
+        CSR[hip].VSSIP[0] = (csr_value >> 1) & ((1 << NUM_VSSI) - 1);
+      }
+
   STIP:
     location: 5
     type: RW-H
     reset_value: UNDEFINED_LEGAL
     alias: hip.VSTIP[0]
     description: |
       *Supervisor Timer Interrupt Pending*
-
       Indicates a pending timer interrupt at the supervisor level.
       Read-only zero when `hideleg[6] == 0`, else aliased to `hip.VSTIP[0]`.
+    "sw_write(csr_value)": |
+      if (CSR[hideleg].ST == 1) {
+        CSR[hip].VSTIP[0] = (csr_value >> 5) & ((1 << NUM_VSTI) - 1);
+      }
 
   SEIP:
     location: 9
@@ -66,9 +79,12 @@ fields:
     alias: hip.VSEIP[0]
     description: |
       *Supervisor External Interrupt Pending*
-
       Indicates a pending external interrupt at the supervisor level.
       Read-only zero when `hideleg[10] == 0`, else aliased to `hip.VSEIP[0]`.
+    "sw_write(csr_value)": |
+      if (CSR[hideleg].SE == 1) {
+        CSR[hip].VSEIP[0] = (csr_value >> 9) & ((1 << NUM_VSEI) - 1);
+      }
 
   LCOFIP:
     location: 13
@@ -77,6 +93,9 @@ fields:
     alias: sip.LCOFIP[0]
     description: |
       *Local Counter Overflow Interrupt Pending*
-
       Indicates an overflow of a local counter.
       Read-only zero when `hideleg[13] == 0`, else aliased to `sip.LCOFIP[0]`.
+    "sw_write(csr_value)": |
+      if (CSR[hideleg].LCOF == 1) {
+        CSR[sip].LCOFIP[0] = (csr_value >> 13) & 0x1;
+      }

arch/csr/Smcntrpmf/mcyclecfg.yaml

@@ -0,0 +1,76 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mcyclecfg
+long_name: Machine Cycle Counter Configuration
+address: 0x321
+priv_mode: M
+length: 64
+definedBy: Smcntrpmf
+description: |
+  The `mcyclecfg` CSR is a 64-bit machine-level register that configures privilege
+  mode filtering for the cycle counter. Each inhibit bit (xINH) suppresses
+  counting of events in the corresponding privilege mode when set.
+
+  | Field   | Description                                             |
+  |---------|---------------------------------------------------------|
+  | MINH    | If set, then counting of events in M-mode is inhibited.       |
+  | SINH    | If set, then counting of events in S/HS-mode is inhibited.    |
+  | UINH    | If set, then counting of events in U-mode is inhibited.       |
+  | VSINH   | If set, then counting of events in VS-mode is inhibited.      |
+  | VUINH   | If set, then counting of events in VU-mode is inhibited.      |
+
+  When all xINH bits are zero, event counting is enabled in all modes.
+
+  For each bit in 61:58, if the associated privilege mode is not implemented,
+  the bit is read-only zero.
+
+  Bit 63 is hardwired to 0, as these counters do not generate overflow interrupts.
+
+  Bits [57:0] are reserved (WPRI) and read as zero.
+
+  For RV32, the upper 32 bits of `mcyclecfg` are accessed via `mcyclecfgh` (CSR 0x721).
+
+  Note: Although CSR address 0x320 would have been a more natural choice,
+  it is already allocated to `mcountinhibit`.
+
+fields:
+  MINH:
+    location: 62
+    base: 64
+    type: RW
+    definedBy: M
+    description: If set, then counting of events in M-mode is inhibited.
+    reset_value: UNDEFINED_LEGAL
+
+  SINH:
+    location: 61
+    base: 64
+    type: RW
+    definedBy: S
+    description: If set, then counting of events in S/HS-mode is inhibited.
+    reset_value: UNDEFINED_LEGAL
+
+  UINH:
+    location: 60
+    base: 64
+    type: RW
+    definedBy: U
+    description: If set, then counting of events in U-mode is inhibited.
+    reset_value: UNDEFINED_LEGAL
+
+  VSINH:
+    location: 59
+    base: 64
+    type: RW
+    definedBy: H
+    description: If set, then counting of events in VS-mode is inhibited.
+    reset_value: UNDEFINED_LEGAL
+
+  VUINH:
+    location: 58
+    base: 64
+    type: RW
+    definedBy: H
+    description: If set, then counting of events in VU-mode is inhibited.
+    reset_value: UNDEFINED_LEGAL

arch/csr/Smcntrpmf/mcyclecfgh.yaml

@@ -0,0 +1,53 @@
+# yaml-language-server: $schema=../../../schemas/csr_schema.json
+$schema: csr_schema.json#
+kind: csr
+name: mcyclecfgh
+long_name: Machine Cycle Counter Configuration High
+address: 0x721
+priv_mode: M
+length: 32
+definedBy: Smcntrpmf
+description: |
+  Upper 32 bits of the 64-bit `mcyclecfg` CSR, used for RV32 systems to access
+  the privilege mode filtering inhibit bits.
+
+fields:
+  MINH:
+    alias: mcyclecfg.MINH
+    location: 30
+    type: RW
+    definedBy: M
+    description: If set, then counting of events in M-mode is inhibited.
+    reset_value: UNDEFINED_LEGAL
+
+  SINH:
+    alias: mcyclecfg.SINH
+    location: 29
+    type: RW
+    definedBy: S
+    description: If set, then counting of events in S/HS-mode is inhibited.
+    reset_value: UNDEFINED_LEGAL
+
+  UINH:
+    alias: mcyclecfg.UINH
+    location: 28
+    type: RW
+    definedBy: U
+    description: If set, then counting of events in U-mode is inhibited.
+    reset_value: UNDEFINED_LEGAL
+
+  VSINH:
+    alias: mcyclecfg.VSINH
+    location: 27
+    type: RW
+    definedBy: H
+    description: If set, then counting of events in VS-mode is inhibited.
+    reset_value: UNDEFINED_LEGAL
+
+  VUINH:
+    alias: mcyclecfg.VUINH
+    location: 26
+    type: RW
+    definedBy: H
+    description: If set, then counting of events in VU-mode is inhibited.
+    reset_value: UNDEFINED_LEGAL