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fix(data): merge definitions for ld/sd (#869)
`ld` and `sd` are defined for both "I" extension (RV64) as well as "Zilsd" extension (RV32). They are currently defined separately for each extension. Merge them. Fixes #821
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‎backends/instructions_appendix/all_instructions.golden.adoc

Lines changed: 46 additions & 68 deletions
Original file line numberDiff line numberDiff line change
@@ -14920,17 +14920,34 @@ Assembly::
1492014920
ld xd, imm(xs1)
1492114921

1492214922
Encoding::
14923+
[NOTE]
14924+
This instruction has different encodings in RV32 and RV64
14925+
14926+
RV32::
14927+
[wavedrom, ,svg,subs='attributes',width="100%"]
14928+
....
14929+
{"reg":[{"bits":7,"name": 0x3,"type":2},{"bits":5,"name": "xd != {1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31}","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": "imm","type":4}]}
14930+
....
14931+
14932+
RV64::
1492314933
[wavedrom, ,svg,subs='attributes',width="100%"]
1492414934
....
1492514935
{"reg":[{"bits":7,"name": 0x3,"type":2},{"bits":5,"name": "xd","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": "imm","type":4}]}
1492614936
....
1492714937

1492814938
Description::
14929-
Load 64 bits of data into register `xd` from an
14939+
For RV64, load 64 bits of data into register `xd` from an
1493014940
address formed by adding `xs1` to a signed offset.
14941+
<% if ext?(:Zilsd) %>
14942+
For RV32, Loads a 64-bit value into registers xd and xd+1.
14943+
The effective address is obtained by adding
14944+
register xs1 to the sign-extended 12-bit offset.
14945+
<% end %>
1493114946

1493214947

1493314948
Decode Variables::
14949+
*RV32:*
14950+
1493414951
[width="100%", cols="1,2", options="header"]
1493514952
|===
1493614953
|Variable Name |Location
@@ -14939,50 +14956,23 @@ Decode Variables::
1493914956
|xd |$encoding[11:7]
1494014957
|===
1494114958

14942-
Included in::
14943-
[options="autowrap,autowidth"]
14944-
|===
14945-
| Extension | Version
14946-
14947-
| *I* | ~> 2.1.0
14948-
14949-
|===
14950-
14951-
14952-
[#udb:doc:inst:ld]
14953-
== ld
14954-
14955-
Synopsis::
14956-
Load doubleword to even/odd register pair
14957-
14958-
Assembly::
14959-
ld xd, offset(xs1)
14960-
14961-
Encoding::
14962-
[wavedrom, ,svg,subs='attributes',width="100%"]
14963-
....
14964-
{"reg":[{"bits":7,"name": 0x3,"type":2},{"bits":5,"name": "xd != {1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31}","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":12,"name": "imm","type":4}]}
14965-
....
14966-
14967-
Description::
14968-
Loads a 64-bit value into registers xd and xd+1. The effective address is obtained by adding
14969-
register xs1 to the sign-extended 12-bit offset.
14970-
14959+
*RV64:*
1497114960

14972-
Decode Variables::
1497314961
[width="100%", cols="1,2", options="header"]
1497414962
|===
1497514963
|Variable Name |Location
14976-
|xd |$encoding[11:7]
14977-
|xs1 |$encoding[19:15]
1497814964
|imm |$encoding[31:20]
14965+
|xs1 |$encoding[19:15]
14966+
|xd |$encoding[11:7]
1497914967
|===
1498014968

1498114969
Included in::
1498214970
[options="autowrap,autowidth"]
1498314971
|===
1498414972
| Extension | Version
1498514973

14974+
| *I* | ~> 2.1.0
14975+
1498614976
| *Zilsd* | ~> 1.0
1498714977

1498814978
|===
@@ -17237,69 +17227,57 @@ Assembly::
1723717227
sd xs2, imm(xs1)
1723817228

1723917229
Encoding::
17230+
[NOTE]
17231+
This instruction has different encodings in RV32 and RV64
17232+
17233+
RV32::
17234+
[wavedrom, ,svg,subs='attributes',width="100%"]
17235+
....
17236+
{"reg":[{"bits":7,"name": 0x23,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": "xs2 != {1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31}","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
17237+
....
17238+
17239+
RV64::
1724017240
[wavedrom, ,svg,subs='attributes',width="100%"]
1724117241
....
1724217242
{"reg":[{"bits":7,"name": 0x23,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": "xs2","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
1724317243
....
1724417244

1724517245
Description::
17246-
Store 64 bits of data from register `xs2` to an
17246+
For RV64, store 64 bits of data from register `xs2` to an
1724717247
address formed by adding `xs1` to a signed offset.
17248+
<% if ext?(:Zilsd) %>
17249+
For RV32, store doubleword from even/odd register pair.
17250+
<% end %>
1724817251

1724917252

1725017253
Decode Variables::
17254+
*RV32:*
17255+
1725117256
[width="100%", cols="1,2", options="header"]
1725217257
|===
1725317258
|Variable Name |Location
17254-
|imm |sext({$encoding[31:25], $encoding[11:7]})
17255-
|xs1 |$encoding[19:15]
17259+
|imm |{$encoding[31:25], $encoding[11:7]}
1725617260
|xs2 |$encoding[24:20]
17261+
|xs1 |$encoding[19:15]
1725717262
|===
1725817263

17259-
Included in::
17260-
[options="autowrap,autowidth"]
17261-
|===
17262-
| Extension | Version
17263-
17264-
| *I* | ~> 2.1.0
17265-
17266-
|===
17267-
17268-
17269-
[#udb:doc:inst:sd]
17270-
== sd
17271-
17272-
Synopsis::
17273-
Store doubleword from even/odd register pair
17274-
17275-
Assembly::
17276-
sd xs2, offset(xs1)
17277-
17278-
Encoding::
17279-
[wavedrom, ,svg,subs='attributes',width="100%"]
17280-
....
17281-
{"reg":[{"bits":7,"name": 0x23,"type":2},{"bits":5,"name": "imm[4:0]","type":4},{"bits":3,"name": 0x3,"type":2},{"bits":5,"name": "xs1","type":4},{"bits":5,"name": "xs2 != {1,3,5,7,9,11,13,15,17,19,21,23,25,27,29,31}","type":4},{"bits":7,"name": "imm[11:5]","type":4}]}
17282-
....
17283-
17284-
Description::
17285-
Stores a 64-bit value from registers xs2 and xs2+1. The effective address is obtained by adding
17286-
register xs1 to the sign-extended 12-bit offset.
17287-
17264+
*RV64:*
1728817265

17289-
Decode Variables::
1729017266
[width="100%", cols="1,2", options="header"]
1729117267
|===
1729217268
|Variable Name |Location
17293-
|xs1 |$encoding[19:15]
17269+
|imm |sext({$encoding[31:25], $encoding[11:7]})
1729417270
|xs2 |$encoding[24:20]
17295-
|imm |{$encoding[31:25], $encoding[11:7]}
17271+
|xs1 |$encoding[19:15]
1729617272
|===
1729717273

1729817274
Included in::
1729917275
[options="autowrap,autowidth"]
1730017276
|===
1730117277
| Extension | Version
1730217278

17279+
| *I* | ~> 2.1.0
17280+
1730317281
| *Zilsd* | ~> 1.0
1730417282

1730517283
|===

‎spec/std/isa/inst/I/ld.yaml

Lines changed: 40 additions & 12 deletions
Original file line numberDiff line numberDiff line change
@@ -8,20 +8,37 @@ kind: instruction
88
name: ld
99
long_name: Load doubleword
1010
description: |
11-
Load 64 bits of data into register `xd` from an
11+
For RV64, load 64 bits of data into register `xd` from an
1212
address formed by adding `xs1` to a signed offset.
13-
definedBy: I
14-
base: 64
13+
<% if ext?(:Zilsd) %>
14+
For RV32, Loads a 64-bit value into registers xd and xd+1.
15+
The effective address is obtained by adding
16+
register xs1 to the sign-extended 12-bit offset.
17+
<% end %>
18+
19+
definedBy:
20+
anyOf: [I, Zilsd]
1521
assembly: xd, imm(xs1)
1622
encoding:
17-
match: -----------------011-----0000011
18-
variables:
19-
- name: imm
20-
location: 31-20
21-
- name: xs1
22-
location: 19-15
23-
- name: xd
24-
location: 11-7
23+
RV32:
24+
match: -----------------011-----0000011
25+
variables:
26+
- name: imm
27+
location: 31-20
28+
- name: xs1
29+
location: 19-15
30+
- name: xd
31+
location: 11-7
32+
not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
33+
RV64:
34+
match: -----------------011-----0000011
35+
variables:
36+
- name: imm
37+
location: 31-20
38+
- name: xs1
39+
location: 19-15
40+
- name: xd
41+
location: 11-7
2542
access:
2643
s: always
2744
u: always
@@ -30,7 +47,18 @@ access:
3047
operation(): |
3148
XReg virtual_address = X[xs1] + $signed(imm);
3249
33-
X[xd] = read_memory<64>(virtual_address, $encoding);
50+
if (xlen() == 32) {
51+
if (implemented?(ExtensionName::Zilsd)) {
52+
Bits<64> data = read_memory<64>(virtual_address, $encoding);
53+
54+
X[xd] = data[31:0];
55+
X[xd+1] = data[63:32];
56+
} else {
57+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
58+
}
59+
} else {
60+
X[xd] = read_memory<64>(virtual_address, $encoding);
61+
}
3462
3563
# SPDX-SnippetBegin
3664
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎spec/std/isa/inst/I/sd.yaml

Lines changed: 38 additions & 13 deletions
Original file line numberDiff line numberDiff line change
@@ -8,30 +8,55 @@ kind: instruction
88
name: sd
99
long_name: Store doubleword
1010
description: |
11-
Store 64 bits of data from register `xs2` to an
11+
For RV64, store 64 bits of data from register `xs2` to an
1212
address formed by adding `xs1` to a signed offset.
13-
definedBy: I
14-
base: 64
13+
<% if ext?(:Zilsd) %>
14+
For RV32, store doubleword from even/odd register pair.
15+
<% end %>
16+
definedBy:
17+
anyOf: [I, Zilsd]
1518
assembly: xs2, imm(xs1)
1619
encoding:
17-
match: -----------------011-----0100011
18-
variables:
19-
- name: imm
20-
location: 31-25|11-7
21-
sign_extend: true
22-
- name: xs1
23-
location: 19-15
24-
- name: xs2
25-
location: 24-20
20+
RV32:
21+
match: -----------------011-----0100011
22+
variables:
23+
- name: imm
24+
location: 31-25|11-7
25+
- name: xs2
26+
not: [1, 3, 5, 7, 9, 11, 13, 15, 17, 19, 21, 23, 25, 27, 29, 31]
27+
location: 24-20
28+
- name: xs1
29+
location: 19-15
30+
RV64:
31+
match: -----------------011-----0100011
32+
variables:
33+
- name: imm
34+
location: 31-25|11-7
35+
sign_extend: true
36+
- name: xs2
37+
location: 24-20
38+
- name: xs1
39+
location: 19-15
2640
access:
2741
s: always
2842
u: always
2943
vs: always
3044
vu: always
3145
operation(): |
46+
Bits<64> data;
3247
XReg virtual_address = X[xs1] + $signed(imm);
3348
34-
write_memory<64>(virtual_address, X[xs2], $encoding);
49+
if (xlen() == 32) {
50+
if (implemented?(ExtensionName::Zclsd)) {
51+
data = {X[xs2 + 1], X[xs2]};
52+
} else {
53+
raise(ExceptionCode::IllegalInstruction, mode(), $encoding);
54+
}
55+
} else {
56+
data = X[xs2];
57+
}
58+
59+
write_memory<64>(virtual_address, data, $encoding);
3560
3661
# SPDX-SnippetBegin
3762
# SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

‎spec/std/isa/inst/Zilsd/ld.yaml

Lines changed: 0 additions & 39 deletions
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