fix(data): fix cases where GPR register file used instead of FPR (#858)

Fixes #777.

Author: ThinkOpenly

backends/instructions_appendix/all_instructions.golden.adoc

@@ -8,8 +8,8 @@ kind: instruction
 name: andn
 long_name: AND with inverted operand
 description: |
-  Performs the bitwise logical AND operation between `rs1` and the
-  bitwise inversion of `rs2`.
+  Performs the bitwise logical AND operation between `xs1` and the
+  bitwise inversion of `xs2`.
 definedBy:
   anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, xs2

spec/std/isa/inst/B/andn.yaml

@@ -15,11 +15,11 @@ assembly: xd, xs1, xs2
 encoding:
   match: 0000101----------001-----0110011
   variables:
-    - name: rs2
+    - name: xs2
       location: 24-20
-    - name: rs1
+    - name: xs1
       location: 19-15
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always
@@ -32,17 +32,17 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  XReg rs1_val = X[rs1];
-  XReg rs2_val = X[rs2];
+  XReg xs1_val = X[xs1];
+  XReg xs2_val = X[xs2];
   XReg output = 0;
 
   for (U32 i=0; i < xlen(); i++) {
-    output = (((rs2_val >> i) & 1) == 1)
-      ? output ^ (rs1_val << i)
+    output = (((xs2_val >> i) & 1) == 1)
+      ? output ^ (xs1_val << i)
       : output;
   }
 
-  X[rd] = output;
+  X[xd] = output;
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/B/clmul.yaml

@@ -15,11 +15,11 @@ assembly: xd, xs1, xs2
 encoding:
   match: 0000101----------011-----0110011
   variables:
-    - name: rs2
+    - name: xs2
       location: 24-20
-    - name: rs1
+    - name: xs1
       location: 19-15
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always
@@ -32,17 +32,17 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  XReg rs1_val = X[rs1];
-  XReg rs2_val = X[rs2];
+  XReg xs1_val = X[xs1];
+  XReg xs2_val = X[xs2];
   XReg output = 0;
 
   for (U32 i=1; i <= xlen(); i++) {
-    output = (((rs2_val >> i) & 1) == 1)
-      ? output ^ (rs1_val >> (xlen() - i))
+    output = (((xs2_val >> i) & 1) == 1)
+      ? output ^ (xs1_val >> (xlen() - i))
       : output;
   }
 
-  X[rd] = output;
+  X[xd] = output;
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/B/clmulh.yaml

@@ -8,18 +8,18 @@ kind: instruction
 name: orn
 long_name: OR with inverted operand
 description: |
-  Performs the bitwise logical OR operation between rs1 and the bitwise inversion of rs2.
+  Performs the bitwise logical OR operation between xs1 and the bitwise inversion of xs2.
 definedBy:
   anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, xs2
 encoding:
   match: 0100000----------110-----0110011
   variables:
-    - name: rs2
+    - name: xs2
       location: 24-20
-    - name: rs1
+    - name: xs1
       location: 19-15
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always
@@ -32,7 +32,7 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  X[rd] = X[rs1] | ~X[rs2];
+  X[xd] = X[xs1] | ~X[xs2];
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/B/orn.yaml

@@ -15,7 +15,7 @@ description: |
 
   [NOTE]
   The byte-reverse operation is only available for the full register width. To emulate word-sized
-  and halfword-sized byte-reversal, perform a `rev8 rd,rs` followed by a `srai rd,rd,K`, where K
+  and halfword-sized byte-reversal, perform a `rev8 xd,xs1` followed by a `srai xd,xd,K`, where K
   is XLEN-32 and XLEN-16, respectively.
 definedBy:
   anyOf: [Zbb, Zbkb]
@@ -24,16 +24,16 @@ encoding:
   RV32:
     match: 011010011000-----101-----0010011
     variables:
-      - name: rs1
+      - name: xs1
         location: 19-15
-      - name: rd
+      - name: xd
         location: 11-7
   RV64:
     match: 011010111000-----101-----0010011
     variables:
-      - name: rs1
+      - name: xs1
         location: 19-15
-      - name: rd
+      - name: xd
         location: 11-7
 access:
   s: always
@@ -46,7 +46,7 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  XReg input = X[rs1];
+  XReg input = X[xs1];
   XReg output = 0;
 
   XReg j = xlen() - 1;
@@ -56,7 +56,7 @@ operation(): |
     j = j - 8;
   }
 
-  X[rd] = output;
+  X[xd] = output;
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/B/rev8.yaml

@@ -8,18 +8,18 @@ kind: instruction
 name: rol
 long_name: Rotate left (Register)
 description: |
-  Performs a rotate left of rs1 by the amount in least-significant `log2(XLEN)` bits of rs2.
+  Performs a rotate left of xs1 by the amount in least-significant `log2(XLEN)` bits of xs2.
 definedBy:
   anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, xs2
 encoding:
   match: 0110000----------001-----0110011
   variables:
-    - name: rs2
+    - name: xs2
       location: 24-20
-    - name: rs1
+    - name: xs1
       location: 19-15
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always
@@ -32,9 +32,9 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  XReg shamt = (xlen() == 32) ? X[rs2][4:0] : X[rs2][5:0];
+  XReg shamt = (xlen() == 32) ? X[xs2][4:0] : X[xs2][5:0];
 
-  X[rd] = (X[rs1] << shamt) | (X[rs1] >> (xlen() - shamt));
+  X[xd] = (X[xs1] << shamt) | (X[xs1] >> (xlen() - shamt));
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/B/rol.yaml

@@ -8,7 +8,7 @@ kind: instruction
 name: rolw
 long_name: Rotate left word (Register)
 description: |
-  Performs a rotate left of the least-significant word of rs1 by the amount in least-significant 5 bits of rs2.
+  Performs a rotate left of the least-significant word of xs1 by the amount in least-significant 5 bits of xs2.
   The resulting word value is sign-extended by copying bit 31 to all of the more-significant bits.
 definedBy:
   anyOf: [Zbb, Zbkb]
@@ -17,11 +17,11 @@ base: 64
 encoding:
   match: 0110000----------001-----0111011
   variables:
-    - name: rs2
+    - name: xs2
       location: 24-20
-    - name: rs1
+    - name: xs1
       location: 19-15
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always
@@ -34,12 +34,12 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  XReg rs1_word = X[rs1][31:0];
-  XReg shamt = X[rs2][4:0];
+  XReg xs1_word = X[xs1][31:0];
+  XReg shamt = X[xs2][4:0];
 
-  XReg unextended_result = (rs1_word << shamt) | (rs1_word >> (32 - shamt));
+  XReg unextended_result = (xs1_word << shamt) | (xs1_word >> (32 - shamt));
 
-  X[rd] = {{32{unextended_result[31]}}, unextended_result};
+  X[xd] = {{32{unextended_result[31]}}, unextended_result};
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/B/rolw.yaml

@@ -8,18 +8,18 @@ kind: instruction
 name: ror
 long_name: Rotate right (Register)
 description: |
-  Performs a rotate right of rs1 by the amount in least-significant `log2(XLEN)` bits of rs2.
+  Performs a rotate right of xs1 by the amount in least-significant `log2(XLEN)` bits of xs2.
 definedBy:
   anyOf: [Zbb, Zbkb]
 assembly: xd, xs1, xs2
 encoding:
   match: 0110000----------101-----0110011
   variables:
-    - name: rs2
+    - name: xs2
       location: 24-20
-    - name: rs1
+    - name: xs1
       location: 19-15
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always
@@ -32,9 +32,9 @@ operation(): |
     raise (ExceptionCode::IllegalInstruction, mode(), $encoding);
   }
 
-  XReg shamt = (xlen() == 32) ? X[rs2][4:0] : X[rs2][5:0];
+  XReg shamt = (xlen() == 32) ? X[xs2][4:0] : X[xs2][5:0];
 
-  X[rd] = (X[rs1] >> shamt) | (X[rs1] << (xlen() - shamt));
+  X[xd] = (X[xs1] >> shamt) | (X[xs1] << (xlen() - shamt));
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

spec/std/isa/inst/B/ror.yaml

@@ -8,7 +8,7 @@ kind: instruction
 name: rori
 long_name: Rotate right (Immediate)
 description: |
-  Performs a rotate right of rs1 by the amount in the least-significant log2(XLEN) bits of shamt.
+  Performs a rotate right of xs1 by the amount in the least-significant log2(XLEN) bits of shamt.
   For RV32, the encodings corresponding to shamt[5]=1 are reserved.
 definedBy:
   anyOf: [Zbb, Zbkb]
@@ -19,18 +19,18 @@ encoding:
     variables:
       - name: shamt
         location: 24-20
-      - name: rs1
+      - name: xs1
         location: 19-15
-      - name: rd
+      - name: xd
         location: 11-7
   RV64:
     match: 011000-----------101-----0010011
     variables:
       - name: shamt
         location: 25-20
-      - name: rs1
+      - name: xs1
         location: 19-15
-      - name: rd
+      - name: xd
         location: 11-7
 access:
   s: always
@@ -45,7 +45,7 @@ operation(): |
 
   XReg shamt = (xlen() == 32) ? shamt[4:0] : shamt[5:0];
 
-  X[rd] = (X[rs1] >> shamt) | (X[rs1] << (xlen() - shamt));
+  X[xd] = (X[xs1] >> shamt) | (X[xs1] << (xlen() - shamt));
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>