fix(data): fix field names to be closer to operands

- `dret`, `mnret`, and `sctrclr` take no operands.
- `sspush` and `sspopchk` are each single mnemonics that take a very
  restricted set of operand values.
  Also include a bit of documentation.
- `vaeskf1.vi`, `vaeskf2.vi`, `vsm3c.vi`, `vsm4k.vi`, `vwsll.vi`:
  renamed field to match operand.

Author: ThinkOpenly

spec/std/isa/inst/Sdext/dret.yaml

@@ -10,7 +10,7 @@ long_name: No synopsis available
 description: |
   No description available.
 definedBy: Sdext
-assembly: dret
+assembly: ""
 encoding:
   match: "01111011001000000000000001110011"
   variables: []

spec/std/isa/inst/Smdbltrp/sctrclr.yaml

@@ -10,7 +10,7 @@ long_name: No synopsis available
 description: |
   No description available.
 definedBy: Smdbltrp
-assembly: sctrclr
+assembly: ""
 encoding:
   match: "00010000010000000000000001110011"
   variables: []

spec/std/isa/inst/Smrnmi/mnret.yaml

@@ -14,7 +14,7 @@ description: |
   also sets mstatus.MPRV to 0. If the Zicfilp extension is implemented, then if the new privileged mode is
   y, MNRET sets ELP to the logical AND of yLPE (see Section 22.1.1) and mnstatus.MNPELP.
 definedBy: Smrnmi
-assembly: mnret
+assembly: ""
 encoding:
   match: "01110000001000000000000001110011"
   variables: []

spec/std/isa/inst/Zicfiss/sspopchk.x1.yaml

@@ -0,0 +1,30 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: sspopchk
+long_name: Shadow Stack Pop
+description: |
+  A shadow stack pop operation is defined as an XLEN wide read from the current
+  top of the shadow stack followed by an increment of the ssp by XLEN/8.
+
+  Only x1 and x5 registers are supported as xs1 for SSPOPCHK.
+definedBy: Zicfiss
+assembly: xs1
+encoding:
+  match: 110011011100-----100000000110011
+  variables:
+    - name: xs1
+      location: 19-15
+      # prettier-ignore
+      not: [ 0, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ]
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

spec/std/isa/inst/Zicfiss/sspopchk.x5.yaml

@@ -0,0 +1,31 @@
+# Copyright (c) Qualcomm Technologies, Inc. and/or its subsidiaries.
+# SPDX-License-Identifier: BSD-3-Clause-Clear
+
+# yaml-language-server: $schema=../../../../schemas/inst_schema.json
+
+$schema: inst_schema.json#
+kind: instruction
+name: sspush
+long_name: Shadow Stack Push
+description: |
+  A shadow stack push operation is defined as decrement of the ssp by XLEN/8
+  followed by a store of the value in the link register to memory at the new
+  top of the shadow stack.
+
+  Only x1 and x5 registers are supported as xs2 for SSPUSH.
+definedBy: Zicfiss
+assembly: xs2
+encoding:
+  match: "1100111-----00000100000001110011"
+  variables:
+    - name: xs2
+      location: 24-20
+      # prettier-ignore
+      not: [ 0, 2, 3, 4, 6, 7, 8, 9, 10, 11, 12, 13, 14, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31 ]
+access:
+  s: always
+  u: always
+  vs: always
+  vu: always
+data_independent_timing: false
+operation(): |

spec/std/isa/inst/Zicfiss/sspopchk.yaml

@@ -18,7 +18,7 @@ encoding:
       location: 25-25
     - name: vs2
       location: 24-20
-    - name: zimm5
+    - name: imm
       location: 19-15
     - name: vd
       location: 11-7