Add IDL for converting 32-bit Floating point number to 32-bit signed and unsigned integer (#756)

Added IDL code, descriptions and long names.

---------

Signed-off-by: Shashank V M <shashankmathew8@gmail.com>
Signed-off-by: Shashank V M <svivekan@qti.qualcomm.com>

Author: ShashankVM

arch/inst/F/fcvt.w.s.yaml

@@ -3,10 +3,10 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.w.s
-long_name: Convert single-precision float to integer word to signed 32-bit integer
+long_name: Convert single-precision float to signed word.
 description: |
-  Converts a floating-point number in floating-point register _fs1_ to a signed 32-bit integer indicates
-  integer register _rd_.
+  Converts a floating-point number in floating-point register _fs1_ to a signed 32-bit integer in
+  integer register _xd_.
 
   For XLEN >32, `fcvt.w.s` sign-extends the 32-bit result to the destination register width.
 
@@ -30,7 +30,7 @@ description: |
   All floating-point to integer and integer to floating-point conversion instructions round
   according to the _rm_ field.
   A floating-point register can be initialized to floating-point positive zero using
-  `fcvt.s.w rd, x0`, which will never set any exception flags.
+  `fcvt.s.w xd, x0`, which will never set any exception flags.
 
   All floating-point conversion instructions set the Inexact exception flag if the rounded
   result differs from the operand value and the Invalid exception flag is not set.
@@ -44,7 +44,7 @@ encoding:
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always
@@ -54,30 +54,8 @@ access:
 data_independent_timing: true
 operation(): |
   check_f_ok($encoding);
-
-  Bits<32> sp_value = f[fs1][31:0];
-
-  Bits<1> sign = sp_value[31];
-  Bits<8> exp = sp_value[30:23];
-  Bits<23> sig = sp_value[22:0];
-
   RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
-
-  if ( (exp == 0xff) && (sig != 0)) {
-    sign = 0;
-    set_fp_flag(FpFlag::NV);
-    X[rd] = SP_CANONICAL_NAN;
-  } else {
-    if (exp != 0) {
-      sig = sig | 0x00800000;
-    }
-    Bits<64> sig64 = sig << 32;
-    Bits<16> shift_dist = 0xAA - exp;
-    if (0 < shift_dist) {
-      sig64 = softfloat_shiftRightJam64(sig64, shift_dist );
-    }
-    X[rd] = softfloat_roundToI32( sign, sig64, rounding_mode );
-  }
+  X[xd] = f32_to_i32(X[fs1], rounding_mode);
 
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>

arch/inst/F/fcvt.wu.s.yaml

@@ -3,19 +3,46 @@
 $schema: "inst_schema.json#"
 kind: instruction
 name: fcvt.wu.s
-long_name: No synopsis available
+long_name: Convert single-precision float to unsigned word.
 description: |
-  No description available.
+  Converts a floating-point number in floating-point register _fs1_ to an unsigned 32-bit integer in integer register _xd_.
+
+  For XLEN >32, `fcvt.wu.s` sign-extends the 32-bit result to the destination register width.
+
+  If the rounded result is not representable as a 32-bit unsigned integer, it is clipped to the
+  nearest value and the invalid flag is set.
+
+  The range of valid inputs and behavior for invalid inputs are:
+
+  [separator="!"]
+  !===
+  ! ! Value
+
+  h! Minimum valid input (after rounding) ! `0`
+  h! Maximum valid input (after rounding) ! `2^32 - 1`
+  h! Output for out-of-range negative input ! `0`
+  h! Output for `-∞` ! `0`
+  h! Output for out-of-range positive input ! `2^32 - 1`
+  h! Output for `+∞` for `NaN` ! `2^32 - 1`
+  !===
+
+  All floating-point to integer and integer to floating-point conversion instructions round
+  according to the _rm_ field.
+  A floating-point register can be initialized to floating-point positive zero using
+  `fcvt.s.w xd, x0`, which will never set any exception flags.
+
+  All floating-point conversion instructions set the Inexact exception flag if the rounded
+  result differs from the operand value and the Invalid exception flag is not set.
 definedBy: F
 assembly: xd, fs1, rm
 encoding:
   match: 110000000001-------------1010011
   variables:
-    - name: rs1
+    - name: fs1
       location: 19-15
     - name: rm
       location: 14-12
-    - name: rd
+    - name: xd
       location: 11-7
 access:
   s: always
@@ -24,7 +51,9 @@ access:
   vu: always
 data_independent_timing: true
 operation(): |
-
+  check_f_ok($encoding);
+  RoundingMode rounding_mode = rm_to_mode(rm, $encoding);
+  X[xd] = f32_to_ui32(X[fs1], rounding_mode);
 # SPDX-SnippetBegin
 # SPDX-FileCopyrightText: 2017-2025 Contributors to the RISCV Sail Model <https://github.com/riscv/sail-riscv/blob/master/LICENCE>
 # SPDX-License-Identifier: BSD-2-Clause

arch/isa/fp.idl

@@ -20,8 +20,15 @@ Bits<32> SP_NEG_ZERO      = 32'b1_00000000_00000000000000000000000;
 Bits<32> SP_CANONICAL_NAN = 32'b0_11111111_10000000000000000000000;
 Bits<16> HP_CANONICAL_NAN = 16'b0_11111_1000000000;
 
-Bits<32> WORD_NEG_OVERFLOW = 32'h8000_0000; # minimum 32-bit integer
-Bits<32> WORD_POS_OVERFLOW = 32'h7FFF_FFFF; # maximum 32-bit integer
+Bits<32> WORD_NEG_OVERFLOW = 32'h8000_0000; # minimum signed 32-bit integer
+Bits<32> WORD_POS_OVERFLOW = 32'h7FFF_FFFF; # maximum signed 32-bit integer
+
+Bits<32> UI32_NEG_OVERFLOW = 32'h0000_0000; # minimum unsigned 32-bit integer
+Bits<32> UI32_POS_OVERFLOW = 32'hFFFF_FFFF; # maximum unsigned 32-bit integer
+
+Bits<32> UI32_NAN          = 32'hFFFF_FFFF; # NaN to unsigned 32-bit integer
+Bits<32> I32_NAN           = 32'h7FFF_FFFF; # NaN to signed 32-bit integer
+
 
 enum RoundingMode {
   RNE 0b000 # Round to Nearest, ties to Even
@@ -331,7 +338,7 @@ function softfloat_roundToI32 {
     Bits<64> sig,
     RoundingMode roundingMode
   description {
-    Round to unsigned 32-bit integer, using +rounding_mode+
+    Round to signed 32-bit integer, using +rounding_mode+
   }
   body {
     Bits<16> roundIncrement = 0x800;
@@ -375,6 +382,58 @@ function softfloat_roundToI32 {
   }
 }
 
+function softfloat_roundToUI32 {
+  returns Bits<32>
+  arguments
+    Bits<1> sign,
+    Bits<64> sig,
+    RoundingMode roundingMode
+  description {
+    Round to unsigned 32-bit integer, using +rounding_mode+
+  }
+  body {
+    Bits<16> roundIncrement = 0x800;
+    if (
+      (roundingMode != RoundingMode::RMM)
+      && (roundingMode != RoundingMode::RNE)
+    ) {
+      roundIncrement = 0;
+      if ( sign == 1) {
+        if (sig == 0) { return 0; }
+        if (roundingMode == RoundingMode::RDN) { set_fp_flag(FpFlag::NV); }
+      } else {
+        if (roundingMode == RoundingMode::RUP) { roundIncrement = 0xFFF; }
+      }
+    }
+
+    Bits<16> roundBits = sig & 0xFFF;
+    sig = sig + roundIncrement;
+    if ((sig & 0xFFFFF00000000000) != 0) {
+      set_fp_flag(FpFlag::NV);
+      return sign == 1 ? UI32_NEG_OVERFLOW : UI32_POS_OVERFLOW;
+    }
+
+    Bits<32> z = sig >> 12;
+    if (
+      (roundBits == 0x800 && (roundingMode == RoundingMode::RNE))
+    ) {
+      z = z & ~32'b1;
+    }
+
+
+
+    if ((z != 0) && (sign == 1)) {
+      set_fp_flag(FpFlag::NV);
+      return sign == 1 ? UI32_NEG_OVERFLOW : UI32_POS_OVERFLOW;
+    }
+
+    if (roundBits != 0) {
+      set_fp_flag(FpFlag::NX);
+    }
+    return z;
+  }
+}
+
 function packToF32UI {
   returns Bits<32>
   arguments
@@ -875,7 +934,7 @@ function i32_to_f32 {
     U32 a,
     RoundingMode mode
   description {
-    Converts 32-bit signed integer to 32-bit floating point
+    Converts 32-bit signed integer to 32-bit floating point number
   }
   body {
     # sign of integer, it is 1 when negative
@@ -894,7 +953,7 @@ function ui32_to_f32 {
     U32 a,
     RoundingMode mode
   description {
-    Converts 32-bit unsigned integer to 32-bit floating point
+    Converts 32-bit unsigned integer to 32-bit floating point number
   }
   body {
     # sign of integer, it is 1 when negative
@@ -908,3 +967,77 @@ function ui32_to_f32 {
     }
   }
 }
+
+function f32_to_i32 {
+  returns U32
+  arguments
+    U32 a,
+    RoundingMode mode
+  description {
+    Converts 32-bit floating point number to a signed 32-bit integer
+  }
+  body {
+    Bits<1> sign = signF32UI(a);
+    Bits<8> exp  = expF32UI(a);
+    Bits<23> sig = fracF32UI(a);
+    Bits<8> shiftDist;
+    U64 sig64;
+    # for NaN return the highest positive value and set floating-point flag to invalid.
+    if ((exp == 8'hFF) && (sig != 0)) {
+      sign = 0;
+      set_fp_flag(FpFlag::NV);
+      return I32_NAN;
+    }
+
+    # MSB of significand is set to 1 because minimum 32-bit integer in IEEE 754 is 32'h80000000
+    if (exp != 0) {
+      sig = sig | 32'h00800000;
+    }
+
+    sig64 = sig `<< 32;
+    shiftDist = 8'hAA - exp;
+
+    if (shiftDist > 0) {
+      sig64 = softfloat_shiftRightJam64( sig64, shiftDist);
+    }
+
+    return softfloat_roundToI32(sign, sig64, mode);
+  }
+}
+
+function f32_to_ui32 {
+  returns U32
+  arguments
+    U32 a,
+    RoundingMode mode
+  description {
+    Converts 32-bit floating point number to an unsigned 32-bit integer
+  }
+  body {
+    Bits<1> sign = signF32UI(a);
+    Bits<8> exp  = expF32UI(a);
+    Bits<23> sig = fracF32UI(a);
+    Bits<8> shiftDist;
+    U64 sig64;
+    # for NaN return the highest positive value and set floating-point flag to invalid.
+    if ((exp == 8'hFF) && (sig != 0)) {
+      sign = 0;
+      set_fp_flag(FpFlag::NV);
+      return UI32_NAN;
+    }
+
+    # MSB of significand is set to 1 because minimum 32-bit integer in IEEE 754 is 32'h80000000
+    if (exp != 0) {
+      sig = sig | 32'h00800000;
+    }
+
+    sig64 = sig `<< 32;
+    shiftDist = 8'hAA - exp;
+
+    if (shiftDist > 0) {
+      sig64 = softfloat_shiftRightJam64( sig64, shiftDist);
+    }
+
+    return softfloat_roundToUI32(sign, sig64, mode);
+  }
+}