Benchmark vec-sgemm fails to build for 32 bit targets due to inline assembly

[LeonThesen]

Trying to compile the tests for a custom rv32im target with softfloat on a riscv toolchain built for this exact target I ran into the following errors while building the vec-sgemm benchmark:

Error: unrecognized opcode ld t0,0(sp)' Error: unrecognized opcode sd s0,0(sp)'

The issue is the fact that vec_sgemm_nn function is written in 64 bit assembly (making use of ld/sd instructions). This effectively ignores the configuration specified by the configure script and what was specified for the make command:

../configure --prefix=/home/leon/tools/riscv-valhalla --with-xlen=32 --host=riscv32-unknown-elf

make RISCV_PREFIX=/home/leon/tools/riscv-valhalla/bin/riscv32-unknown-elf-
XLEN=32
MARCH=rv32im
ABI=ilp32

The toolchain was built with:
../configure --prefix=$RISCV_PREFIX --with-arch=rv32im --with-abi=ilp32 --disable-multilib

A possible solution would be to supply an additional 32 bit version of the assembly file vec-sgemm.S next to the 64 bit version.

[LeonThesen]

If the benchmark is not intended to be used by 32 bit targets the XLEN=32 option could ignore the vec-sgemm benchmark automatically.