Cache hierarchy design

[h0lyalg0rithm]

I have started this discussion so we can gather different ideas regarding the cache design.
From the issue I have the following

• Add counters for occupancy of fill buffer and hits on fill.
• Keep data copy for execution-driven model
• API design (user input)for user configurable cache
• Design standard cache L1, L2, L3 model

[ghost]

Keep data copy for execution-driven model

This is great forward-thinking to support a future execution-driven simulation modeling (EDM). However, there are other ways to represent the data path for EDM that do not require the data to be copied into the performance model's cache.

I have written a few EDM simulators in my past and one of them did perform the copies. It was a nightmare. 😆 Ensuring the data was coherent between cores in a multi-core simulation in addition to the overhead in copying the data over and over again significantly outweighed the benefits of keeping it local. There is another path... 😉

[ghost]

Sparta Cache Model: https://github.com/sparcians/map/tree/master/sparta/cache

[egieske]

Should a new private member variable be added to MemAccessInfo to record which unit or in_port initiated the MemAccessInfo or is wrapping MemAccessInfo with a nested class to add such information preferred?
Both the L2MMU and L2Cache may receive requests from multiple units, (e.g., L2MMU requests come from either the ITLB or DTLB or a L2Cache request may come from the IL1, DL1, or L2 MMU and neither MemAccessInfo nor Inst seem to presently have a clean way to track which of the potential requesting units initiated a given MemAccessInfo. It isn't clear to me that adding a member to the generally available MemAccessInfo class is the correct way to enable this. Altenatively the L2MMU or L2Cache could do as LSU, which has a nested class, LoadStoreAccessInfo, to add information to MemAccessInfo for instructions it is executing.

[ghost]

I anticipate MemAccessInfo class to grow in complexity and details as the MSS design of Olympia morphs. For example, the originator of the access (I-side/D-side, I-side L1 miss, D-side L1 miss, etc). Agreed this information will be required when returning the response.