Merge branch 'riscv-software-src:master' into jatin/spike-stf-dockerfile

Author: Jatin-exe

core/Inst.cpp

@@ -1,24 +1,33 @@
 // <Inst.cpp> -*- C++ -*-
 
 #include "Inst.hpp"
+#include "rename/RenameData.hpp"
+#include "CoreUtils.hpp"
 #include <unordered_map>
 
 namespace olympia
 {
-    const std::unordered_map<Inst::Status,std::string> Inst::status2String = {
-        { Inst::Status::BEFORE_FETCH,"BEFORE_FETCH" },
-        { Inst::Status::FETCHED,     "FETCHED"      },
-        { Inst::Status::DECODED,     "DECODED"      },
-        { Inst::Status::RENAMED,     "RENAMED"      },
-        { Inst::Status::DISPATCHED,  "DISPATCHED"   },
-        { Inst::Status::SCHEDULED,   "SCHEDULED"    },
-        { Inst::Status::COMPLETED,   "COMPLETED"    },
-        { Inst::Status::RETIRED,     "RETIRED"      },
-        { Inst::Status::FLUSHED,     "FLUSHED"      },
-        { Inst::Status::UNMOD,       "UNMOD"        },
-        { Inst::Status::FUSED,       "FUSED"        },
-        { Inst::Status::FUSION_GHOST,"FUSION_GHOST" }
-    };
+    const std::unordered_map<Inst::Status, std::string> Inst::status2String = {
+        {Inst::Status::BEFORE_FETCH, "BEFORE_FETCH"},
+        {Inst::Status::FETCHED, "FETCHED"},
+        {Inst::Status::DECODED, "DECODED"},
+        {Inst::Status::RENAMED, "RENAMED"},
+        {Inst::Status::DISPATCHED, "DISPATCHED"},
+        {Inst::Status::SCHEDULED, "SCHEDULED"},
+        {Inst::Status::COMPLETED, "COMPLETED"},
+        {Inst::Status::RETIRED, "RETIRED"},
+        {Inst::Status::FLUSHED, "FLUSHED"},
+        {Inst::Status::UNMOD, "UNMOD"},
+        {Inst::Status::FUSED, "FUSED"},
+        {Inst::Status::FUSION_GHOST, "FUSION_GHOST"}};
+
+    RenameData::OpInfoWithRegfile::OpInfoWithRegfile(const OpInfoList::value_type & op_info) :
+        field_value(op_info.field_value),
+        field_id(op_info.field_id),
+        reg_file(coreutils::determineRegisterFile(op_info)),
+        is_x0(field_value == 0 && reg_file == core_types::RF_INTEGER)
+    { }
+
 
     bool isCallInstruction(const mavis::OpcodeInfo::PtrType & opcode_info)
     {
@@ -48,6 +57,17 @@ namespace olympia
         return false;
     }
 
+    template<class OpInfoListType>
+    OpInfoListType getOpcodeInfoWithRegFileInfo(const Inst::OpInfoList & mavis_opcode_info)
+    {
+        OpInfoListType op_list;
+        for (const auto & op : mavis_opcode_info)
+        {
+            op_list.emplace_back(op);
+        }
+        return op_list;
+    }
+
     /*!
      * \brief Construct an Instruction
      * \param opcode_info    Mavis Opcode information
@@ -61,7 +81,13 @@ namespace olympia
                const InstArchInfo::PtrType & inst_arch_info, const sparta::Clock* clk) :
         opcode_info_(opcode_info),
         inst_arch_info_(inst_arch_info),
+        dest_opcode_info_with_reg_file_(
+            getOpcodeInfoWithRegFileInfo<RenameData::DestOpInfoWithRegfileList>(opcode_info_->getDestOpInfoList())),
+        src_opcode_info_with_reg_file_(
+            getOpcodeInfoWithRegFileInfo<RenameData::SrcOpInfoWithRegfileList>(opcode_info_->getSourceOpInfoList())),
         is_store_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::STORE)),
+        is_load_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::LOAD)),
+        is_move_(opcode_info->isInstTypeAnyOf(mavis::OpcodeInfo::InstructionTypes::MOVE)),
         is_transfer_(miscutils::isOneOf(inst_arch_info_->getTargetPipe(),
                                         InstArchInfo::TargetPipe::I2F,
                                         InstArchInfo::TargetPipe::F2I)),
@@ -71,6 +97,7 @@ namespace olympia
         is_csr_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::CSR)),
         is_return_(isReturnInstruction(opcode_info)),
         has_immediate_(opcode_info_->hasImmediate()),
+        rob_targeted_(getPipe() == InstArchInfo::TargetPipe::ROB),
         is_vector_(opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::VECTOR)),
         is_vector_whole_reg_(
             is_vector_ && opcode_info->isInstType(mavis::OpcodeInfo::InstructionTypes::WHOLE)),
@@ -82,8 +109,8 @@ namespace olympia
 
         // Check that instruction is supported
         sparta_assert(getPipe() != InstArchInfo::TargetPipe::UNKNOWN,
-            "Unknown target pipe (execution) for " << getMnemonic());
+                      "Unknown target pipe (execution) for " << getMnemonic());
         sparta_assert(getExecuteTime() != 0,
-            "Unknown execution time (latency) for " << getMnemonic());
+                      "Unknown execution time (latency) for " << getMnemonic());
     }
 } // namespace olympia

core/Inst.hpp

@@ -5,6 +5,7 @@
 #include "sparta/memory/AddressTypes.hpp"
 #include "sparta/resources/Scoreboard.hpp"
 #include "sparta/resources/Queue.hpp"
+#include "sparta/resources/Buffer.hpp"
 #include "sparta/pairs/SpartaKeyPairs.hpp"
 #include "sparta/simulation/State.hpp"
 #include "sparta/utils/SpartaSharedPointer.hpp"
@@ -17,6 +18,7 @@
 #include "CoreTypes.hpp"
 #include "vector/VectorConfig.hpp"
 #include "MiscUtils.hpp"
+#include "rename/RenameData.hpp"
 
 #include <cstdint>
 #include <cstdlib>
@@ -38,47 +40,12 @@ namespace olympia
     class Inst
     {
       public:
-        class RenameData
-        {
-          public:
-            // A register consists of its value and its register file.
-            struct Reg
-            {
-                uint32_t val = 0;
-                core_types::RegFile rf = core_types::RegFile::RF_INVALID;
-                mavis::InstMetaData::OperandFieldID field_id =
-                    mavis::InstMetaData::OperandFieldID::NONE;
-                bool is_x0 = false;
-            };
-
-            using RegList = std::vector<Reg>;
-
-            void setOriginalDestination(const Reg & destination) { original_dest_ = destination; }
-
-            void setDestination(const Reg & destination) { dest_ = destination; }
-
-            void setDataReg(const Reg & data_reg) { data_reg_ = data_reg; }
-
-            void setSource(const Reg & source) { src_.emplace_back(source); }
-
-            const RegList & getSourceList() const { return src_; }
-
-            const Reg & getOriginalDestination() const { return original_dest_; }
-
-            const Reg & getDestination() const { return dest_; }
-
-            const Reg & getDataReg() const { return data_reg_; }
-
-          private:
-            Reg original_dest_;
-            Reg dest_;
-            RegList src_;
-            Reg data_reg_;
-        };
-
         // Used by Mavis
         using PtrType = sparta::SpartaSharedPointer<Inst>;
 
+        // Used by Rename, etc
+        using WeakPtrType = sparta::SpartaWeakPointer<Inst>;
+
         // The modeler needs to alias a type called
         // "SpartaPairDefinitionType" to the Pair Definition class of
         // itself
@@ -229,12 +196,9 @@ namespace olympia
 
         bool hasTail() const { return has_tail_; }
 
-        void setUOpParent(sparta::SpartaWeakPointer<olympia::Inst> & parent_uop)
-        {
-            parent_uop_ = parent_uop;
-        }
+        void setUOpParent(WeakPtrType & parent_uop) { parent_uop_ = parent_uop; }
 
-        sparta::SpartaWeakPointer<olympia::Inst> getUOpParent() { return parent_uop_; }
+        WeakPtrType getUOpParent() { return parent_uop_; }
 
         // Branch instruction was taken (always set for JAL/JALR)
         void setTakenBranch(bool taken) { is_taken_branch_ = taken; }
@@ -252,6 +216,14 @@ namespace olympia
 
         bool isLastInFetchBlock() const { return last_in_fetch_block_; }
 
+        // ROB target information
+        void setTargetROB(bool tgt = true) { rob_targeted_ = tgt; }
+
+        bool isTargetROB() const
+        {
+            return rob_targeted_;
+        }
+
         // Opcode information
         std::string getMnemonic() const { return opcode_info_->getMnemonic(); }
 
@@ -272,7 +244,20 @@ namespace olympia
             return opcode_info_->getSourceOpInfoList();
         }
 
-        const OpInfoList & getDestOpInfoList() const { return opcode_info_->getDestOpInfoList(); }
+        const OpInfoList & getDestOpInfoList() const
+        {
+            return opcode_info_->getDestOpInfoList();
+        }
+
+        const RenameData::DestOpInfoWithRegfileList & getDestOpInfoListWithRegfile() const
+        {
+            return dest_opcode_info_with_reg_file_;
+        }
+
+        const RenameData::SrcOpInfoWithRegfileList & getSrcOpInfoListWithRegfile() const
+        {
+            return src_opcode_info_with_reg_file_;
+        }
 
         bool hasZeroRegSource() const
         {
@@ -284,7 +269,7 @@ namespace olympia
         bool hasZeroRegDest() const
         {
             return std::any_of(getDestOpInfoList().begin(), getDestOpInfoList().end(),
-                               [](const mavis::OperandInfo::Element & elem)
+                               [](const auto & elem)
                                { return elem.field_value == 0; });
         }
 
@@ -318,9 +303,57 @@ namespace olympia
             }
         }
 
+        void setDataRegister(RenameData::Reg && reg)
+        {
+            if (!reg.op_info.is_x0)
+            {
+                getDataRegisterBitMask(reg.op_info.reg_file).set(reg.phys_reg);
+            }
+            getRenameData().setDataReg(std::forward<RenameData::Reg>(reg));
+        }
+
+        void setDestRegisterBitWithScoreboardUpdate(const RenameData::Reg & reg,
+                                                    sparta::Scoreboard* const scoreboard)
+        {
+            auto & bitmask = getDestRegisterBitMask(reg.op_info.reg_file);
+            bitmask.set(reg.phys_reg);
+
+            // clear scoreboard for the PRF we are allocating
+            scoreboard->clearBits(bitmask);
+        }
+
+        void addDestRegister(RenameData::Reg && reg)
+        {
+            getRenameData().addDestination(std::forward<RenameData::Reg>(reg));
+        }
+
+        void addDestRegisterWithScoreboardUpdate(RenameData::Reg && reg,
+                                                 sparta::Scoreboard* const scoreboard)
+        {
+            if (!reg.op_info.is_x0)
+            {
+                setDestRegisterBitWithScoreboardUpdate(reg, scoreboard);
+            }
+
+            addDestRegister(std::forward<RenameData::Reg>(reg));
+        }
+
+        void addSrcRegister(RenameData::Reg && reg)
+        {
+            if (!reg.op_info.is_x0)
+            {
+                getSrcRegisterBitMask(reg.op_info.reg_file).set(reg.phys_reg);
+            }
+
+            getRenameData().addSource(std::forward<RenameData::Reg>(reg));
+        }
+
+
         // Static instruction information
         bool isStoreInst() const { return is_store_; }
 
+        bool isLoadInst() const { return is_load_; }
+
         bool isLoadStoreInst() const { return inst_arch_info_->isLoadStore(); }
 
         uint32_t getExecuteTime() const { return inst_arch_info_->getExecutionTime(); }
@@ -357,6 +390,14 @@ namespace olympia
 
         bool isCoF() const { return is_cof_; }
 
+        bool isMove() const { return is_move_; }
+
+        // Is a load the producer for one or more of this inst's operands?
+        bool hasLoadProducer() const { return has_load_producer_; }
+
+        // This instruction is fed by a load
+        void setLoadProducer(bool load_producer) { has_load_producer_ = load_producer; }
+
         // Rename information
         core_types::RegisterBitMask & getSrcRegisterBitMask(const core_types::RegFile rf)
         {
@@ -433,6 +474,11 @@ namespace olympia
         mavis::OpcodeInfo::PtrType opcode_info_;
         InstArchInfo::PtrType inst_arch_info_;
 
+        // Handy list that extends Mavis' opcode info with register
+        // file type.
+        RenameData::DestOpInfoWithRegfileList dest_opcode_info_with_reg_file_;
+        RenameData::SrcOpInfoWithRegfileList  src_opcode_info_with_reg_file_;
+
         sparta::memory::addr_t inst_pc_ = 0; // Instruction's PC
         sparta::memory::addr_t target_vaddr_ =
             0; // Instruction's Target PC (for branches, loads/stores)
@@ -443,6 +489,8 @@ namespace olympia
         uint64_t program_id_increment_ = 1;
         bool is_speculative_ = false; // Is this instruction soon to be flushed?
         const bool is_store_;
+        const bool is_load_;
+        const bool is_move_;
         const bool is_transfer_; // Is this a transfer instruction (F2I/I2F)
         const bool is_branch_;
         const bool is_condbranch_;
@@ -453,6 +501,11 @@ namespace olympia
         bool is_cof_ = false;
         const bool has_immediate_;
 
+        // Is this instruction just retired? (Dynamically assigned)
+        bool rob_targeted_ = false;
+
+        bool has_load_producer_ = false;
+
         // Vector
         const bool is_vector_;
         const bool is_vector_whole_reg_;
@@ -489,7 +542,9 @@ namespace olympia
     };
 
     using InstPtr = Inst::PtrType;
+    using InstWeakPtr = Inst::WeakPtrType;
     using InstQueue = sparta::Queue<InstPtr>;
+    using InstBuffer = sparta::Buffer<InstPtr>;
 
     inline std::ostream & operator<<(std::ostream & os, const Inst::Status & status)
     {

core/InstArchInfo.cpp

@@ -31,6 +31,7 @@ namespace olympia
         {"vload", InstArchInfo::TargetPipe::VLOAD},
         {"vstore", InstArchInfo::TargetPipe::VSTORE},
         {"vset", InstArchInfo::TargetPipe::VSET},
+        {"rob", InstArchInfo::TargetPipe::ROB},
         {"sys", InstArchInfo::TargetPipe::SYS},
         {"?", InstArchInfo::TargetPipe::UNKNOWN}};
 
@@ -60,6 +61,7 @@ namespace olympia
         {InstArchInfo::TargetPipe::VLOAD, "VLOAD"},
         {InstArchInfo::TargetPipe::VSTORE, "VSTORE"},
         {InstArchInfo::TargetPipe::VSET, "VSET"},
+        {InstArchInfo::TargetPipe::ROB, "ROB"},
         {InstArchInfo::TargetPipe::SYS, "SYS"},
         {InstArchInfo::TargetPipe::UNKNOWN, "?"}};
 

core/InstArchInfo.hpp

@@ -62,6 +62,7 @@ namespace olympia
             VLOAD,
             VSTORE,
             VSET,
+            ROB,
             SYS,
             UNKNOWN
         };