resovling comments and push again

Author: MayneMei

core/lsu/LSU.cpp

@@ -33,7 +33,7 @@ namespace olympia
         cache_read_stage_(cache_lookup_stage_
                           + 1), // Get data from the cache in the cycle after cache lookup
         complete_stage_(
-            cache_read_stage_  
+            cache_read_stage_
             + p->cache_read_stage_length), // Complete stage is after the cache read stage
         ldst_pipeline_("LoadStorePipeline", (complete_stage_ + 1),
                        getClock()), // complete_stage_ + 1 is number of stages
@@ -505,7 +505,7 @@ namespace olympia
             return;
         }
 
-        // Loads dont perform a cache lookup if there are older stores haven't issued in the load store queue
+        // The Load doesn't perform a cache lookup if there are older stores haven't issued in the load store queue
         if (!inst_ptr->isStoreInst() && !allOlderStoresIssued_(inst_ptr)
             && allow_speculative_load_exec_)
         {

core/lsu/LSU.hpp

@@ -76,12 +76,6 @@ namespace olympia
 
         //! name of this resource.
         static const char name[];
-
-        // return allow_data_forwarding for test
-        bool allow_data_forwarding_ex() {
-            return allow_data_forwarding_;
-        }
-
         ////////////////////////////////////////////////////////////////////////////////
         // Type Name/Alias Declaration
         ////////////////////////////////////////////////////////////////////////////////

docs/design_document_template/LSU.adoc

@@ -45,7 +45,7 @@
 
 == OVERVIEW
 
-The Load Store Unit (LSU) implements the memory interface for the Olympia processor, managing all load and store operations. It features multiple parallel pipelines, data forwarding capabilities, and ensures memory consistency while maintaining high performance through careful hazard management and efficient queueing structures.
+The Load Store Unit (LSU) implements the memory interface for the Olympia processor. Managing all load and store operations. The LSU features multiple parallel pipelines, data forwarding capabilities, and ensures memory consistency while maintaining high performance through careful hazard management and efficient queueing structures.
 
 === Overview Block Diagram