From 08f10c58d717b9117bcaa8ac2a23aa020f67ec0c Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sat, 15 Mar 2025 13:07:05 -0500 Subject: [PATCH 1/2] Add Svrsw60t59b extension --- riscv/encoding.h | 3 ++- riscv/isa_parser.h | 1 + riscv/mmu.cc | 4 ++++ 3 files changed, 7 insertions(+), 1 deletion(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index bcc1ace2dc..3cf934ceb5 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -458,7 +458,8 @@ #define PTE_A 0x040 /* Accessed */ #define PTE_D 0x080 /* Dirty */ #define PTE_SOFT 0x300 /* Reserved for Software */ -#define PTE_RSVD 0x1FC0000000000000 /* Reserved for future standard use */ +#define PTE_SVRSW60T59B 0x1800000000000000 /* Svrsw60t59b: Reserved for software use */ +#define PTE_RSVD 0x07C0000000000000 /* Reserved for future standard use */ #define PTE_PBMT 0x6000000000000000 /* Svpbmt: Page-based memory types */ #define PTE_N 0x8000000000000000 /* Svnapot: NAPOT translation contiguity */ #define PTE_ATTR 0xFFC0000000000000 /* All attributes and reserved bits */ diff --git a/riscv/isa_parser.h b/riscv/isa_parser.h index fae729ca42..2f55e09678 100644 --- a/riscv/isa_parser.h +++ b/riscv/isa_parser.h @@ -43,6 +43,7 @@ typedef enum { EXT_SVNAPOT, EXT_SVPBMT, EXT_SVINVAL, + EXT_SVRSW60T59B, EXT_ZDINX, EXT_ZFA, EXT_ZFBFMIN, diff --git a/riscv/mmu.cc b/riscv/mmu.cc index c8d6f25552..4484413f49 100644 --- a/riscv/mmu.cc +++ b/riscv/mmu.cc @@ -435,6 +435,8 @@ reg_t mmu_t::s2xlate(reg_t gva, reg_t gpa, access_type type, access_type trap_ty if (pte & PTE_RSVD) { break; + } else if (!proc->extension_enabled(EXT_SVRSW60T59B) && (pte & PTE_SVRSW60T59B)) { + break; } else if (!proc->extension_enabled(EXT_SVNAPOT) && (pte & PTE_N)) { break; } else if (!pbmte && (pte & PTE_PBMT)) { @@ -539,6 +541,8 @@ reg_t mmu_t::walk(mem_access_info_t access_info) if (pte & PTE_RSVD) { break; + } else if (!proc->extension_enabled(EXT_SVRSW60T59B) && (pte & PTE_SVRSW60T59B)) { + break; } else if (!proc->extension_enabled(EXT_SVNAPOT) && (pte & PTE_N)) { break; } else if (!pbmte && (pte & PTE_PBMT)) { From cd3dea8f41e869e18a3dfaa972ac047ded34fe87 Mon Sep 17 00:00:00 2001 From: Ved Shanbhogue Date: Sat, 22 Mar 2025 13:17:26 -0500 Subject: [PATCH 2/2] Update with generated encoding.h --- riscv/encoding.h | 12 ++++++++++-- 1 file changed, 10 insertions(+), 2 deletions(-) diff --git a/riscv/encoding.h b/riscv/encoding.h index 3cf934ceb5..04e2cf222d 100644 --- a/riscv/encoding.h +++ b/riscv/encoding.h @@ -4,7 +4,7 @@ /* * This file is auto-generated by running 'make' in - * https://github.com/riscv/riscv-opcodes (8899b32) + * https://github.com/riscv/riscv-opcodes (fe002a9) */ #ifndef RISCV_CSR_ENCODING_H @@ -1744,8 +1744,14 @@ #define MASK_VFNCVT_X_F_W 0xfc0ff07f #define MATCH_VFNCVT_XU_F_W 0x48081057 #define MASK_VFNCVT_XU_F_W 0xfc0ff07f +#define MATCH_VFNCVTBF16_F_F_Q 0x480c9057 +#define MASK_VFNCVTBF16_F_F_Q 0xfc0ff07f #define MATCH_VFNCVTBF16_F_F_W 0x480e9057 #define MASK_VFNCVTBF16_F_F_W 0xfc0ff07f +#define MATCH_VFNCVTBF16_SAT_F_F_Q 0x480d9057 +#define MASK_VFNCVTBF16_SAT_F_F_Q 0xfc0ff07f +#define MATCH_VFNCVTBF16_SAT_F_F_W 0x480f9057 +#define MASK_VFNCVTBF16_SAT_F_F_W 0xfc0ff07f #define MATCH_VFNMACC_VF 0xb4005057 #define MASK_VFNMACC_VF 0xfc00707f #define MATCH_VFNMACC_VV 0xb4001057 @@ -2968,7 +2974,6 @@ #define INSN_FIELD_IMM4 0xf00000 #define INSN_FIELD_IMM5 0x1f00000 #define INSN_FIELD_IMM6 0x3f00000 -#define INSN_FIELD_ZIMM 0xf8000 #define INSN_FIELD_OPCODE 0x7f #define INSN_FIELD_FUNCT7 0xfe000000 #define INSN_FIELD_VD 0xf80 @@ -3650,7 +3655,10 @@ DECLARE_INSN(vfncvt_rtz_x_f_w, MATCH_VFNCVT_RTZ_X_F_W, MASK_VFNCVT_RTZ_X_F_W) DECLARE_INSN(vfncvt_rtz_xu_f_w, MATCH_VFNCVT_RTZ_XU_F_W, MASK_VFNCVT_RTZ_XU_F_W) DECLARE_INSN(vfncvt_x_f_w, MATCH_VFNCVT_X_F_W, MASK_VFNCVT_X_F_W) DECLARE_INSN(vfncvt_xu_f_w, MATCH_VFNCVT_XU_F_W, MASK_VFNCVT_XU_F_W) +DECLARE_INSN(vfncvtbf16_f_f_q, MATCH_VFNCVTBF16_F_F_Q, MASK_VFNCVTBF16_F_F_Q) DECLARE_INSN(vfncvtbf16_f_f_w, MATCH_VFNCVTBF16_F_F_W, MASK_VFNCVTBF16_F_F_W) +DECLARE_INSN(vfncvtbf16_sat_f_f_q, MATCH_VFNCVTBF16_SAT_F_F_Q, MASK_VFNCVTBF16_SAT_F_F_Q) +DECLARE_INSN(vfncvtbf16_sat_f_f_w, MATCH_VFNCVTBF16_SAT_F_F_W, MASK_VFNCVTBF16_SAT_F_F_W) DECLARE_INSN(vfnmacc_vf, MATCH_VFNMACC_VF, MASK_VFNMACC_VF) DECLARE_INSN(vfnmacc_vv, MATCH_VFNMACC_VV, MASK_VFNMACC_VV) DECLARE_INSN(vfnmadd_vf, MATCH_VFNMADD_VF, MASK_VFNMADD_VF)