From a3feb90af78628b68f7beb0f3117d7373734a896 Mon Sep 17 00:00:00 2001 From: Tony Liu Date: Tue, 21 Jan 2025 14:58:25 +0800 Subject: [PATCH] Fix envcfg check when S-mode is not available --- riscv/csrs.cc | 1 + riscv/decode_macros.h | 2 +- 2 files changed, 2 insertions(+), 1 deletion(-) diff --git a/riscv/csrs.cc b/riscv/csrs.cc index 2267f7f47d..c943b63fd5 100644 --- a/riscv/csrs.cc +++ b/riscv/csrs.cc @@ -1846,6 +1846,7 @@ ssp_csr_t::ssp_csr_t(processor_t* const proc, const reg_t addr, const reg_t mask void ssp_csr_t::verify_permissions(insn_t insn, bool write) const { masked_csr_t::verify_permissions(insn, write); DECLARE_XENVCFG_VARS(SSE); + auto p = proc; // To match macro usage require_envcfg(SSE); } diff --git a/riscv/decode_macros.h b/riscv/decode_macros.h index 807ad9887f..69039aacae 100644 --- a/riscv/decode_macros.h +++ b/riscv/decode_macros.h @@ -193,7 +193,7 @@ static inline bool is_aligned(const unsigned val, const unsigned pos) #define require_envcfg(field) \ do { \ if (((STATE.prv != PRV_M) && (m##field == 0)) || \ - ((STATE.prv == PRV_U && !STATE.v) && (s##field == 0))) \ + (p->extension_enabled('S') && (STATE.prv == PRV_U && !STATE.v) && (s##field == 0))) \ throw trap_illegal_instruction(insn.bits()); \ else if (STATE.v && ((h##field == 0) || \ ((STATE.prv == PRV_U) && (s##field == 0)))) \