From 11ea86993c7ee36707982471dc1932ca6c0789e6 Mon Sep 17 00:00:00 2001
From: linzhida <linzhida19@mails.ucas.ac.cn>
Date: Tue, 23 Jul 2024 17:20:58 +0800
Subject: [PATCH] medeleg: the 3rd bit of medeleg is unwritable when Sdtrig
 exist.

---
 riscv/csrs.cc | 2 +-
 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/riscv/csrs.cc b/riscv/csrs.cc
index 3fc44e01b1..6340b10731 100644
--- a/riscv/csrs.cc
+++ b/riscv/csrs.cc
@@ -934,7 +934,7 @@ bool medeleg_csr_t::unlogged_write(const reg_t val) noexcept {
     | (1 << CAUSE_MISALIGNED_FETCH)
     | (1 << CAUSE_FETCH_ACCESS)
     | (1 << CAUSE_ILLEGAL_INSTRUCTION)
-    | (1 << CAUSE_BREAKPOINT)
+    | (proc->extension_enabled(EXT_SDTRIG) ? 0 : (1 << CAUSE_BREAKPOINT))
     | (1 << CAUSE_MISALIGNED_LOAD)
     | (1 << CAUSE_LOAD_ACCESS)
     | (1 << CAUSE_MISALIGNED_STORE)